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Webinar Replay – Designing and Verifying HBM ESD Protection Networks

Webinar Replay – Designing and Verifying HBM ESD Protection Networks
by Tom Simon on 08-03-2020 at 10:00 am

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Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More


Free Webinar on Verifying On-Chip ESD Protection

Free Webinar on Verifying On-Chip ESD Protection
by Tom Simon on 06-03-2020 at 6:00 am

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Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to… Read More


Webinar on Transient Simulation of Power Transistors in Converter Circuits

Webinar on Transient Simulation of Power Transistors in Converter Circuits
by Tom Simon on 04-13-2020 at 6:00 am

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Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency… Read More


Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability

Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability
by Tom Simon on 02-20-2020 at 10:00 am

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PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs, or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages.

Due to their size and internal complexity PowerMOS … Read More


WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
by Daniel Nenni on 12-06-2019 at 6:00 am

The symbol for a PowerMOS device in a converter circuit schematic looks simple enough. However, it belies a great deal of hidden complexity. A single device is actually a huge array of parallel intrinsic devices connected together to act as a single high power device. While their gate lengths are small, as with many other MOS devices,… Read More


Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th
by Daniel Nenni on 09-24-2019 at 10:00 am

With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou… Read More


Adding CDM Protection to a Real World LNA Test Case

Adding CDM Protection to a Real World LNA Test Case
by Tom Simon on 08-06-2019 at 6:00 am

In RF designs Low Noise Amplifiers (LNA) play a critical role in system operation. They simultaneously need to be extremely sensitive and noise free, yet also must be able to withstand strong signal input without distortion. LNA designers often struggle to meet device performance specifications. Their task is further complicated… Read More


The Flash and the Taiwan ESD Seminar!

The Flash and the Taiwan ESD Seminar!
by Daniel Nenni on 07-24-2019 at 6:00 am

During my trip through Asia last week I attended the Taiwan ESD Workshop. Hsinchu is densely populated with some of the smartest semiconductor people in the world so it is well worth the trip, absolutely.  As it turns out ESD is one of the top concerns in semiconductor design and manufacture. The current rule based and simulation … Read More


HBM or CDM ESD Verification – You Need Both

HBM or CDM ESD Verification – You Need Both
by Tom Simon on 07-11-2019 at 11:00 am

In the realm of ESD protection, Charged Device Model (CDM) is becoming the biggest challenge. Of course, Human Body Model (HBM) is still essential, and needs to be used when verifying chips. However, a number of factors are raising the potential losses that CDM events can cause relative to HBM. These factors fall into two categories:… Read More


Upcoming HBM and CDM ESD Verification Seminar in Taiwan

Upcoming HBM and CDM ESD Verification Seminar in Taiwan
by Tom Simon on 06-25-2019 at 10:00 am

The electrostatic discharge that occurs in lightening, as seen in the picture below, can cause serious damage to the objects on the ground. Over centuries mankind has devised ways, such as lighting rods and arresters, to deflect the energy so it is dissipated harmlessly. The same drama plays out on modern semiconductors due to … Read More