During my trip through Asia last week I attended the Taiwan ESD Workshop. Hsinchu is densely populated with some of the smartest semiconductor people in the world so it is well worth the trip, absolutely. As it turns out ESD is one of the top concerns in semiconductor design and manufacture. The current rule based and simulation solutions are not scaling so the search is on for new ways to protect our chips from electrostatic discharge.
The DC Comics character the Flash (my personal favorite) received his super powers when he was struck by lightning in his lab. Sadly, in real life neither people nor electronic circuits are so lucky when they are hit with lightning. Even nature’s scaled down common electrostatic discharges can have devastating effects on modern integrated circuit chips. Far from imbuing them with super powers, electrostatic discharges (ESD) render chips useless, by destroying devices and melting metal interconnect, or more insidiously damaging them just enough to make it into a product that will mysteriously fail down the road.
To avoid this peril designers employ protection circuits that have to operate as fast as the Flash to intervene and prevent damage. Their ability to protect the circuit comes from having a lightning fast response to an incoming ESD event, harmlessly deflecting the high voltage current before it can cause any harm to the circuit. The actual behavior and performance of the ESD protection designed into a chip depends on many factors. Last week in Taiwan, Magwel’s CEO, Dundar Dumlugol, presented a well attended seminar on the topic of ESD protection simulation, where he talked about many of the specific factors that play a role in determining ESD protection effectiveness.
In the case of HBM, Dundar suggested that despite a few minor disadvantages, a static simulation based approach offers both high throughput and very high accuracy for ESD simulation. When done properly, static simulation can tell designers about voltage build up over devices and also parasitic resistances. It is also good at determining voltage build up over protected devices, parasitic currents in sneak paths, non-uniform triggering of parallel power clamps and non-uniform triggering in fingers of ESD devices. Finally, one of the most important pieces of information that it can provide is the result of competitive triggering between ESD devices and protected devices. This would make the Flash proud, because his mission is to protect those in danger.
Dundar also spoke about how Magwel’s ESDi, used for HBM simulation, takes advantage of reduced order modeling (ROM) to make simulation of large power and ground net resistive networks feasible. Without this approach complete simulation of all the pad pairs in a large design could take many times longer. Using their simulation approach, Magwel’s ESDi can help find the following issues:
- Missing / undersized vias (via burnout)
- Current crowding in metal / vias
- Excessive bus resistance
- Excessive voltage stress over protected devices
- Wrong/missing ESD devices
- ESD device burnout (It2, Vt2 limit check)
- Imbalanced current distribution over the fingers inside ESD devices
- Protected device triggering before parallel ESD device
- Parasitic junction/ Bipolar triggering/ break-down
- Protected device damage (oxide breakdown, junction / device burnout) due to voltage stress & parasitic currents
CDM is a different animal altogether, due to much faster ESD impulses and the potential for damage almost anywhere in the chip. Given this complexity, it seems like the skills of a super hero are needed to predict the outcome of an ESD event. For CDM it turns out that dynamic simulation is the best approach. According to Dundar, you still need a very accurate extracted model for the large nets in the design. This is where the charge is stored prior to a discharge event. The dynamic simulation needs to take into consideration this charge and how it flows through the wire towards the port that is zapped. The voltage drop along the connected nets caused by IR drop can damage protected devices, unless there is sufficient ESD protection designed into the circuit.
Dundar covered one example of an RF LNA circuit test chip provided by Qorvo where the lack of protection diodes caused the discharge to trigger and then pass through an output NFET, leading to its failure. Magwel’s CDMi product predicted this failure, which was confirmed in silicon. Resimulating with added protection diodes shows how the ESD current flows safely to ground. Using this method, it is possible to add only the needed number of protection diodes, preserving output performance.
To learn more register for this webinar replay: Avoiding CDM (Charged Device Model) ESD Failures
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com