The electrostatic discharge that occurs in lightening, as seen in the picture below, can cause serious damage to the objects on the ground. Over centuries mankind has devised ways, such as lighting rods and arresters, to deflect the energy so it is dissipated harmlessly. The same drama plays out on modern semiconductors due to electrostatic build up on people, equipment or the devices themselves. MOS semiconductor devices can easy be damaged or destroyed by the currents and voltages that occur in discharge events during fabrication, assembly or handling.
The very first MOS devices could be destroyed simply by handling them with bare hands. Over the years, on-chip ESD protection has improved dramatically. However, nearly every semiconductor device needs to contain ESD protection circuitry. Properly designed protection networks are transparent during normal operation but are triggered when the device is exposed to an ESD discharge event. Designing these protections is a complex task and verifying them can also be a challenge. While most circuit designers leave the job of designing and verifying the ESD protections to ESD experts, it behooves all designers to understand the design considerations and trade-offs in ESD protection methods.
In Taiwan on July 16th interested engineers and managers will be able attend a seminar organized by Prof. Ming-Dou Ker, where Magwel Chairman and CEO Dundar Dumlugol will discuss the challenges of chip level ESD verification. The presentation will outline each of the steps involved in taking the layout of a chip and modeling it for CDM and HBM simulation. These steps include detailed resistance extraction of the involved nets. Then for HBM and CDM, either TLP or vf-TLP models are used for the ESD devices. Because of snap-back behavior in ESD devices, SPICE simulation is not an option. Dr Dumlugol will discuss the optimal static and dynamic simulation methods for both HBM and CDM.
In addition to triggering intended ESD devices, ESD events can cause triggering of parasitic sneak paths, and parasitic Bipolars. Failure modes can include electromigration and voltage overstress. ESD events can also cross between power domains. ESD protection failures can affect IO devices and devices in the chip’s core. Dr. Dumlugol will discuss these various failure modes and ways that they can be detected before tapeout.
The Seminar is titled “Simulation Based Chip-Level Verification Methodology Of HBM and CDM Events” and will be held July 16th at Hsinchu Jiaotong University in Taiwan from 1:30 PM to 4:30 PM. At the end there will be a question and answer period. Seating is limited and advance registration is available online at http://www.alab.ee.nctu.edu.tw/~esd/reg.html
The seminar will include a demonstration using the techniques discussed in the presentation. This seminar is unique opportunity for learning about the risks and the underlying mechanisms of ESD failures, as well as practical techniques to prevent them in finished silicon. Here is a link to the PDF invitation download.
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com