In RF designs Low Noise Amplifiers (LNA) play a critical role in system operation. They simultaneously need to be extremely sensitive and noise free, yet also must be able to withstand strong signal input without distortion. LNA designers often struggle to meet device performance specifications. Their task is further complicated by the need to add ESD protection to these highly tuned and sensitive circuits. HBM protection shields circuits from pin-to-pin discharge events, and the methodology for adding these protections is fairly straightforward.
CDM events are typically more difficult to characterize and prevent. CDM events occur much more rapidly than HBM events, which means that HBM protections will not respond quickly enough to be useful. To make matters worse, LNA circuits often use thin-film NFETs, which are more likely to be damaged at lower voltages by CDM events.
In an upcoming webinar on CDM protection network analysis, Magwel will mention a real world case involving Qorvo LNA test chips. Qorvo has shown that Magwel’s CDMi solution for evaluating the effectiveness of CDM protections correctly predicted over-voltage damage in a test chip.
The challenge is to add sufficient protection without adding parasitics that would impair circuit performance. In the Qorvo case study, it was shown that designers can determine the optimal protection diode sizing that offers adequate protection and preserves LNA performance.
Initially, the CDM simulation was run with insufficient protection diodes. The error report from Magwel’s CDMi tool shows over-voltage on one of the thin-film NFETs. Qorvo tested physical parts and performed imaging to pin-point the location of the failure, which agrees with the analysis.
Attendees of webinar replay will receive a copy of the case study for their own reference. The webinar should provide insight into an effective solution to the challenges of designing and verifying CDM protection for a range of circuit types.
Failures during manufacturing and assembly or in the field caused by charged device model (CDM) type ESD events are a serious concern for IC design teams. CDM failures are generally caused by charge build up on device packages, which capacitively charge large internal nets, such as GND or VSS. Once a device pin contacts a current path, the charged internal net can discharge through triggered devices to the pin. ESD protection devices allow this to occur harmlessly. However, if the ESD protection network does not work as intended, dangerously high voltages and currents can affect protected devices in the IC.
The only reliable method of determining if ESD protections will be effective is simulation. However, conventional circuit simulation is difficult to set up, too slow and provides hard to interpret results for CDM events. Magwel has developed a simulation based solution specifically designed to address CDM discharge events.
In this webinar you will learn how Magwel’s CDMi efficiently models the complex behavior of a CDM event in an integrated circuit. CDMi uses vf-TLP models in conjunction with 3D solver based resistive network extraction and dynamic simulation to predict device triggering. The results are comprehensive reporting of discharge event voltage and current flows. We will show how CDMi enables CDM ESD signoff before tape out to ensure high product quality and improved yields.
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com