WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation

WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation
by Daniel Nenni on 06-09-2020 at 10:00 am

Verifying the Electrostatic Discharge (ESD) protection network on an IC can be challenging, and if it is not done correctly it can lead to failures on the tester, reduced product reliability or shortened field life. In this webinar you will learn how Magwel’s ESDi thoroughly analyzes all pad combinations in a design for comprehensive… Read More

June 3, 2020July 6, 2020

Free Webinar on Verifying On-Chip ESD Protection

Free Webinar on Verifying On-Chip ESD Protection
by Tom Simon on 06-03-2020 at 6:00 am
Categories: EDA, Events, Magwel

Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to… Read More

September 24, 2019September 27, 2019

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th
by Daniel Nenni on 09-24-2019 at 10:00 am
Categories: EDA, Magwel

With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou… Read More

SemiWiki WEBINAR: Avoiding Charged Device Model ESD Failure

SemiWiki WEBINAR: Avoiding Charged Device Model ESD Failure
by Daniel Nenni on 08-14-2019 at 10:00 am

Failures during manufacturing and assembly or in the field caused by charged device model (CDM) type ESD events are a serious concern for IC design teams. CDM failures are generally caused by charge build-up on device packages, which capacitively charge large internet nets, such as GND or VSS. Once a device pin contacts a current… Read More

August 6, 2019August 19, 2019

Adding CDM Protection to a Real World LNA Test Case

Adding CDM Protection to a Real World LNA Test Case
by Tom Simon on 08-06-2019 at 6:00 am
Categories: EDA, Events, Magwel

In RF designs Low Noise Amplifiers (LNA) play a critical role in system operation. They simultaneously need to be extremely sensitive and noise free, yet also must be able to withstand strong signal input without distortion. LNA designers often struggle to meet device performance specifications. Their task is further complicated… Read More

July 24, 2019August 17, 2019

The Flash and the Taiwan ESD Seminar!

The Flash and the Taiwan ESD Seminar!
by Daniel Nenni on 07-24-2019 at 6:00 am
Categories: EDA, Events, Magwel

During my trip through Asia last week I attended the Taiwan ESD Workshop. Hsinchu is densely populated with some of the smartest semiconductor people in the world so it is well worth the trip, absolutely. As it turns out ESD is one of the top concerns in semiconductor design and manufacture. The current rule based and simulation … Read More

June 3, 2019March 10, 2020

A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation

A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation
by Tom Simon on 06-03-2019 at 8:00 am
Categories: EDA, Magwel, Uncategorized

Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these models work just fine for most purposes. The one important… Read More

August 23, 2018

Verifying ESD Fixes Faster with Incremental Analysis

Verifying ESD Fixes Faster with Incremental Analysis
by Tom Simon on 08-23-2018 at 12:00 pm
Categories: EDA, Magwel

The author of this article, Dündar Dumlugöl, is CEO of Magwel. He has 25 years of experience in EDA managing the development of leading products used for circuit simulation and high-level system design.

Every designer knows how tedious it can be to shuttle back and forth between their layout tool and analysis tools. Every time an… Read More

April 25, 2018

Electrical Reliability Verification – Now At FullChip

Electrical Reliability Verification – Now At FullChip
by Alex Tan on 04-25-2018 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

Advanced process technology offers both device and interconnect scaling for increased design density and higher performance while invoking also significant implementation complexities. Aside from the performance, power and area (PPA) aspects, designer is getting entrenched with the need of tackling more reliability … Read More

April 5, 2018

Stress and Aging

Stress and Aging
by Bernard Murphy on 04-05-2018 at 12:00 pm
Categories: ANSYS, Inc., Automotive, EDA

These failings aren’t just a cross we humans bear; they’re also a concern for chips, particularly in electrical over-stress (EOS) and aging of the circuitry. Such concerns are not new, but they are taking on new urgency given the high reliability and long lifetime expectations we have for safety-critical components in cars and… Read More

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Tag: esd

WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation

Free Webinar on Verifying On-Chip ESD Protection

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th

SemiWiki WEBINAR: Avoiding Charged Device Model ESD Failure

Adding CDM Protection to a Real World LNA Test Case

The Flash and the Taiwan ESD Seminar!

A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation

Verifying ESD Fixes Faster with Incremental Analysis

Electrical Reliability Verification – Now At FullChip

Stress and Aging

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