Failures during manufacturing and assembly or in the field caused by charged device model (CDM) type ESD events are a serious concern for IC design teams. CDM failures are generally caused by charge build-up on device packages, which capacitively charge large internet nets, such as GND or VSS. Once a device pin contacts a current… Read More
Adding CDM Protection to a Real World LNA Test Case
In RF designs Low Noise Amplifiers (LNA) play a critical role in system operation. They simultaneously need to be extremely sensitive and noise free, yet also must be able to withstand strong signal input without distortion. LNA designers often struggle to meet device performance specifications. Their task is further complicated… Read More
The Flash and the Taiwan ESD Seminar!
During my trip through Asia last week I attended the Taiwan ESD Workshop. Hsinchu is densely populated with some of the smartest semiconductor people in the world so it is well worth the trip, absolutely. As it turns out ESD is one of the top concerns in semiconductor design and manufacture. The current rule based and simulation … Read More
A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation
Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these models work just fine for most purposes. The one important… Read More
Verifying ESD Fixes Faster with Incremental Analysis
The author of this article, Dündar Dumlugöl, is CEO of Magwel. He has 25 years of experience in EDA managing the development of leading products used for circuit simulation and high-level system design.
Every designer knows how tedious it can be to shuttle back and forth between their layout tool and analysis tools. Every time an… Read More
Electrical Reliability Verification – Now At FullChip
Advanced process technology offers both device and interconnect scaling for increased design density and higher performance while invoking also significant implementation complexities. Aside from the performance, power and area (PPA) aspects, designer is getting entrenched with the need of tackling more reliability … Read More
Stress and Aging
These failings aren’t just a cross we humans bear; they’re also a concern for chips, particularly in electrical over-stress (EOS) and aging of the circuitry. Such concerns are not new, but they are taking on new urgency given the high reliability and long lifetime expectations we have for safety-critical components in cars and… Read More
Robust Reliability Verification – A Critical Addition To Baseline Checks
Design process retargeting is acommon recurrence based on scaling orBOM(Bill-Of-Material) cost improvement needs. This occursnot only with the availability of foundry process refresh to a more advanced node,but also to any new derivative process node tailored towards matching design complexity, power profile or reliability… Read More
Snapback behavior determines ESD protection effectiveness
Terms like avalanche breakdown and impact ionization sound like they come from the world of science fiction. They do indeed come from a high stakes world, but one that plays out over and over again here and now, on a microscopic scale in semiconductor devices – namely as part of electrostatic discharge (ESD) protection. Semiconductor… Read More
Reliability Signoff for FinFET Designs
Ansys recently hosted a webinar on reliability signoff for FinFET-based designs, spanning thermal, EM, ESD, EMC and aging effects. I doubt you’re going to easily find a more comprehensive coverage of reliability impact and analysis solutions. If you care about reliability in FinFET designs, you might want to check out this webinar.… Read More
