CEO Interview: Stephen Fairbanks of Certus Semiconductor

CEO Interview: Stephen Fairbanks of Certus Semiconductor
by Daniel Nenni on 01-20-2023 at 6:00 am

Stephen Fairbanks headshot 1 1

Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight… Read More


Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?

Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?
by Maxim Ershov on 12-12-2022 at 6:00 am

Fig 1

Resistance checks between ESD diode cells and pads or power clamps, and current density analysis for such current flows are commonly used for ESD networks verification [1]. When such simulations use standard post-layout netlists generated by parasitic extraction tools, the calculated resistances may be dramatically higher… Read More


Webinar: EMI and ESD Simulation of an Entire Electronic Device

Webinar: EMI and ESD Simulation of an Entire Electronic Device
by Admin on 12-05-2022 at 2:02 pm

This webinar, the 4th in a 5-part series, explores the use of EMA3D tools in conjunction with other Ansys computational electromagnetic simulation tools for modeling and simulating EMI effects in entire electronic systems. Integrations between EMA3D products and other Ansys tools, solver technology details, and the ability

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Methods for Current Density and Point-to-point Resistance Calculations

Methods for Current Density and Point-to-point Resistance Calculations
by Daniel Payne on 05-26-2022 at 10:00 am

ESD path min

IC reliability is an issue that circuit design engineers and reliability engineers are concerned about, because physical effects like high Current Density (CD) in interconnect layers, or high point-to-point (P2P) resistance on device interconnect can impact reliability, timing or Electrostatic Discharge (ESD) robustness.… Read More


Redefining ESD signoff (once again) with Pathfinder-SC

Redefining ESD signoff (once again) with Pathfinder-SC
by Admin on 08-11-2021 at 8:14 am

Time:
August 31, 2021
11:30 AM EDT / 4:30 PM BST / 9 PM IST

Venue:
Online

About this Webinar

As semiconductors move into the wafer-scale chip and chiplet era, there is increased focus on the power thermal and reliability area. One of the key aspects of reliability is ESD. While this phenomenon is understood at a higher-level, comprehending… Read More


Magwel Adds Core Device Checking for ESD Verification

Magwel Adds Core Device Checking for ESD Verification
by Tom Simon on 05-11-2021 at 10:00 am

ESDi-XL Core checking

In the past ESD sign-off has been accomplished by a combination of techniques. Often ESD experts are asked to look at a design and assess its ESD robustness based on experience gained from prior chips. Alternatively, designers are told to work with a set of rules given to them, again based on previous experience about what usually… Read More


Webinar Replay – Designing and Verifying HBM ESD Protection Networks

Webinar Replay – Designing and Verifying HBM ESD Protection Networks
by Tom Simon on 08-03-2020 at 10:00 am

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Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More


WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation

WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation
by Daniel Nenni on 06-04-2020 at 7:22 am

Verifying the Electrostatic Discharge (ESD) protection network on an IC can be challenging, and if it is not done correctly it can lead to failures on the tester, reduced product reliability or shortened field life. In this webinar you will learn how Magwel’s ESDi thoroughly analyzes all pad combinations in a design for comprehensive… Read More


Free Webinar on Verifying On-Chip ESD Protection

Free Webinar on Verifying On-Chip ESD Protection
by Tom Simon on 06-03-2020 at 6:00 am

Promo Ad 400x400 1

Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to… Read More


Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th
by Daniel Nenni on 09-24-2019 at 10:00 am

With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou… Read More