Conservative design rules and constraints are often used in reliability verification flows. By combining the leading solutions provided by Siemens Calibre PERC and SPICE simulation technologies, SPICE-accurate full-chip simulation becomes possible in a compelling flow for design teams looking to better understand their
Dan is joined by Stephen Fairbanks, CEO of Certus Semiconductor. Stephen is an ESD pioneer with over 30 years of experience starting with his time at Intel, SRF Technologies, and now Certus Semiconductor.
Stephen describes the varied challenges of ESD andI/O library design presented by today’s technologies and design… Read More
The semiconductor industry continues to drive innovation and constantly seeks methods to lower costs and improve performance. The advantages of custom I/O libraries versus free libraries can be seen as cost-savings or, more importantly, new markets, new customers, and new business
opportunities.
At DAC 2023, Certus Semiconductor… Read More
Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight… Read More
Resistance checks between ESD diode cells and pads or power clamps, and current density analysis for such current flows are commonly used for ESD networks verification [1]. When such simulations use standard post-layout netlists generated by parasitic extraction tools, the calculated resistances may be dramatically higher… Read More
IC reliability is an issue that circuit design engineers and reliability engineers are concerned about, because physical effects like high Current Density (CD) in interconnect layers, or high point-to-point (P2P) resistance on device interconnect can impact reliability, timing or Electrostatic Discharge (ESD) robustness.… Read More
In the past ESD sign-off has been accomplished by a combination of techniques. Often ESD experts are asked to look at a design and assess its ESD robustness based on experience gained from prior chips. Alternatively, designers are told to work with a set of rules given to them, again based on previous experience about what usually… Read More
Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More
Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to… Read More
With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou… Read More
