AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down

AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down
by Robert Maire on 02-19-2024 at 10:00 am

HBM SIP

– AMAT slightly better than expected, flat & guides flat but > expected
– Expects better 2024- Systems flat, service up, display down
– China risk remains high at 45%- $200M Sculpta expected in 2024
– HBM 5% of industry but not a lot of tool sales- but high growth

Still bumping along with flattish Read More


LRCX- In line Q4 & flat guide- No recovery yet- China still 40%- Lags Litho

LRCX- In line Q4 & flat guide- No recovery yet- China still 40%- Lags Litho
by Robert Maire on 01-29-2024 at 6:00 am

Lam Research LCRX

– Lam reported as expected and guided flat- No recovery yet
– Some mix shifts but China still 40% (8X US at 5%)-NVM still low
– HBM is promising but Lam needs a broad memory recovery
– Lam has not seen order surge ASML saw- Likely lagging by 3-4 QTRs

An in line quarter and uninspiring flat guide for Q1

As compared… Read More


SEMICON West 2023 Summary – No recovery in sight – Next Year?

SEMICON West 2023 Summary – No recovery in sight – Next Year?
by Robert Maire on 07-15-2023 at 6:00 am

Semicon west 2023

-SEMICON well attended but bouncing along the biz bottom
-Recovery seems at least a year away with memory even more
-AI creates hope but not impactful- Disconnect tween stocks & reality
-AMAT me too platform- Back end benefits from chiplets

SEMICON busy but subdued

SEMICON is certainly back to pre-covid levels or perhaps better.… Read More


Three Ways to Meet Manufacturing Rules in Advanced Package Designs

Three Ways to Meet Manufacturing Rules in Advanced Package Designs
by Kendall Hiles on 09-15-2022 at 10:00 am

1

Often designers are amazed at the diversity of requirements fabricators and manufacturers have for metal filled areas in advanced package designs. Package fabricators and manufacturers do not like solid metal planes or large metal areas. Their strict metal fill requirements address two main issues. The dielectric and metal… Read More


Upcoming Webinar: 3DIC Design from Concept to Silicon

Upcoming Webinar: 3DIC Design from Concept to Silicon
by Kalar Rajendiran on 01-26-2022 at 10:00 am

Lessons from Existing Multi Die Solutions

Multi-die design is not a new concept. It has been around for a long time and has evolved from 2D level integration on to 2.5D and then to full 3D level implementations. Multiple driving forces have led to this progression.  Whether the forces are driven by market needs, product needs, manufacturing technology availability or EDA… Read More


Optimize AI Chips with Embedded Analytics

Optimize AI Chips with Embedded Analytics
by Kalar Rajendiran on 09-02-2021 at 6:00 am

Tessent Embedded Analytics Architecture

The foundry model, multi-source IP blocks, advanced packaging technologies, cloud computing, hyper-connectivity and access to open-source software have all contributed to the incredible electronics products of recent times. Along with this, the complexity of developing and taking a chip to market has also increased. And… Read More


Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks

Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks
by Tom Simon on 07-06-2021 at 9:00 am

Improved PPA Using 3D IC

The move to true 3D IC, monolithic 3D SOC and 3D heterogeneous integration may require one of the most major design tool architecture overhauls since IC design tools were first developed. While we have been taking steps toward 3DIC with 2.5D designs with interposers, HBM, etc., the fundamental tools and flows remain intact in many… Read More


Magwel Adds Core Device Checking for ESD Verification

Magwel Adds Core Device Checking for ESD Verification
by Tom Simon on 05-11-2021 at 10:00 am

ESDi-XL Core checking

In the past ESD sign-off has been accomplished by a combination of techniques. Often ESD experts are asked to look at a design and assess its ESD robustness based on experience gained from prior chips. Alternatively, designers are told to work with a set of rules given to them, again based on previous experience about what usually… Read More


Enabling Next Generation Silicon In Package Products

Enabling Next Generation Silicon In Package Products
by Kalar Rajendiran on 04-15-2021 at 10:00 am

System on Package Motivation AlphaWave IP

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More


Verification IP Coverage

Verification IP Coverage
by Daniel Nenni on 10-12-2020 at 6:00 am

Truechip SemiWiki 2020

I am pleased to introduce Truechip to the SemiWiki community. Truechip is a leader in the IP Verification – Design and Verification solutions market, one of the fastest growing market segments we track. Truechip has been serving customers for more than 10​ years specialization in VIP integration, customization and SOC Verification.… Read More