Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm

2025 TSMC Revenue by Platform

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show… Read More


A tower-like heterogeneous packaging architecture for the AI era

A tower-like heterogeneous packaging architecture for the AI era
by Moh Kolb on 06-16-2026 at 6:00 am

Picture1 VTEMC

For years, advanced packaging has been described mostly in planar terms: chiplets placed side by side, connected through interposers, bridges, redistribution layers, substrates, and short-reach electrical links. This view remains important. It supports today’s GPU, HBM, chiplet, and 2.5D integration architectures.… Read More


From Evidence to Authority: Bounded Gate Authority for Governed Semiconductor Realization

From Evidence to Authority: Bounded Gate Authority for Governed Semiconductor Realization
by Moh Kolb on 06-09-2026 at 6:00 am

Picture1 BGA JUne2

Advanced semiconductor systems are no longer limited by a single engineering domain. They are constrained by the convergence of many interdependent vectors: silicon nodes, advanced packaging architectures, substrate materials, platform PCBs, power-delivery networks, thermal behavior, manufacturing variation, firmware… Read More


Alchip Accelerates on AI ASIC Demand

Alchip Accelerates on AI ASIC Demand
by Daniel Nenni on 06-04-2026 at 8:00 am

Alchip Accelerates on AI ASIC Demand

Alchip Technologies reported improved financial results for the first quarter, reflecting continued momentum in advanced artificial intelligence (AI), high-performance computing (HPC), and custom ASIC demand. The company cited stronger customer engagement in leading-edge semiconductor designs and accelerating tape-out… Read More


What Winemakers and Chip Designers Have in Common

What Winemakers and Chip Designers Have in Common
by Daniel Nenni on 05-22-2026 at 6:00 am

What Winemakers and Chip Designers Have in Common

Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem,… Read More


Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the InterconnectRead More


Arteris Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplets

Arteris Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplets
by Daniel Nenni on 01-22-2026 at 6:00 am

Smart NoC Automation Accelerating AI Ready SoC Design in the Era of Chiplet

As semiconductor design pushes into increasingly complex territory, driven by Ai, ML, HPC, and heterogeneous system architectures, designers are challenged to balance performance, power, and time-to-market pressures. In this landscape, network-on-chip (NoC) architectures have emerged as a foundational building block… Read More


Signal Integrity Verification Using SPICE and IBIS-AMI

Signal Integrity Verification Using SPICE and IBIS-AMI
by Daniel Payne on 12-15-2025 at 10:00 am

IBIS AMI min

High-speed signals enable electronic systems by using memory interfaces, SerDes channels, data center backplanes and connectivity in automobiles.  Challenges arise from signal distortions like inter-symbol interference, channel loss and dispersion effects. Multi-gigabit data transfer rates in High-Bandwidth Memory… Read More


eBook on Mastering AI Chip Complexity: Pathways to First-Pass Silicon Success

eBook on Mastering AI Chip Complexity: Pathways to First-Pass Silicon Success
by Admin on 09-01-2025 at 8:00 am

MArtering AI Chip Complexity Synopsys

The rapid evolution of artificial intelligence (AI) is transforming industries, from autonomous vehicles to data centers, demanding unprecedented computational power and efficiency. As highlighted in Synopsys’ guide, the global AI chip market is projected to reach $383 billion by 2032, growing at a 38% CAGR. This … Read More


Revolutionizing Chip Packaging: The Impact of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB)

Revolutionizing Chip Packaging: The Impact of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB)
by Admin on 08-27-2025 at 10:00 am

Intel Foundry Packaging Evolution 2025

In an era dominated by artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC), the demand for semiconductors that deliver high data throughput, low latency, and energy efficiency has never been greater. Traditional chip designs often struggle to keep pace with these requirements, leading… Read More