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Coupled Electro-thermal Analysis Essential for PowerMOS Design

Coupled Electro-thermal Analysis Essential for PowerMOS Design
by Tom Simon on 11-08-2018 at 12:00 pm

Power device designers know that when they see a deceptively simple pair of PowerMOS device symbols in the output stage of a power converter circuit schematic, they are actually looking at a massively complex network of silicon and metal interconnect. The corresponding physical devices can have a total device W on the order of meters, making it impossible to treat as a single device. Instead PowerMOS devices have to be analyzed as hundreds or perhaps thousands of smaller devices, connected by a complex web of metallization. The first and most significant effect of this is non-uniform switching, with gate voltage varying across the device during device turn on. This in turn leads to Ids concentrating in some areas and not others.


Transient electrical analysis is capable of showing detailed gate voltages and current densities during the transitions, when typically devices experience their highest power draw. However, there is a second dimension to the problem that influences the electrical analysis – intrinsic device behavior is temperature dependent. As a result, device current values will rise as temperature rises, and the reciprocal is true, temperature will rise as more current flows. In the worst case, this vicious circle may lead to temperature related device failure when metal melts and shorts out the junction.

Thermal dynamics depend of the properties of the die, the surrounding package and even the board. Uncoupled electrical and thermal analysis will have difficulty converging on an accurate solution at each step during circuit operation. To help shed light on this phenomenon, Magwel has a write up of a test case that illustrates how concurrent electro-thermal analysis of PowerMOS devices can predict thermal runaway. The interesting point in their write up is how the package, specifically the shape of the CU-Clip, affects where the damaging thermal problems may occur.

Magwel’s PTM-ET (Power Transistor Modeler – Electro-Thermal) uses thermal properties, thermal boundary conditions, solver based metal extraction and foundry supplied intrinsic device models to drive its concurrent electro-thermal solver to report and visualize voltage, current density and temperature across a PowerMOS device given initial conditions and stimulus.

The Magwel article is informative because it shows a concrete example where temperature rise induces increased current. On a time scale of a few hundred milliseconds after gate voltage is applied the simulation shows temperatures reach past the melting point of aluminum. The PTM-ET Field View offers easy to interpret output for each simulated time step. The write up is available on the Magwel website.

About Magwell
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com