In the realm of ESD protection, Charged Device Model (CDM) is becoming the biggest challenge. Of course, Human Body Model (HBM) is still essential, and needs to be used when verifying chips. However, a number of factors are raising the potential losses that CDM events can cause relative to HBM. These factors fall into two categories: ESD event causes and effects, and difficulty predicting in advance if ESD protections are sufficient and effective. Let’s address each of these in turn.
HBM contemplates an individual pin coming in contact with a charged object, such as a person’s hands. The other requisite condition is that there is a path to ground on another pin. Of course, there might be multiple pins affected in a single real-world event, but testing can be compartmentalized down to two pins at a time. With automated handling, individual ICs are rarely handled by human hands, reducing the likelihood that a pin will be exposed to electrostatic charge.
Even so, protections against HBM type events are very important for chip yield and reliability. There are many other scenarios, during handling and in the field where a device might face a high current ESD discharge. HBM testing can also serve as a proxy for other types of ESD related events. So, we see there is a continued need for adding and verifying protections for HBM.
On the other hand, automated chip handling can subject IC packages to tribo-electric charging as they move through the manufacturing and board assembly processes. This charge build-up can cause big problems once a ground path becomes available. Most often this occurs when one or more pins come in contact with grounded metal. Unlike HBM, the discharge can occur nearly anywhere in the IC. When the package is charged, it induces a capacitive charge build up on large nets on the IC itself. Stored charge is distributed along these nets and any capacitive devices connected to them. Once a conduction path is created large amounts of stored charge begin to flow along these wires. Voltage gradients created during discharge events can subject ESD and core devices to large voltage differentials. Also, even though CDM current pulses are very short their amplitudes can be large leading to thermal failures in thin wires and in triggered devices.
Leading edge designs have several traits that increase the severity of CDM issues. Large IC’s create the need for bigger packages, which can accumulate more charge. The same can be said for the larger nets found in these designs. Additionally, supply nets in FinFET designs are longer and narrower than in earlier nodes. During discharge events, large voltage gradients can occur across these nets, which can damage the smaller and more sensitive advanced node devices.
Both HBM and CDM create challenges for verification teams prior to tape out. Some issues are common to both types of events, others arise or are exacerbated by the nature of CDM events. ESD discharge events are dynamic by their very nature. One or more devices may trigger. It is important to make a full accounting of which devices are actually triggered. Current flows and voltages will be highly dependent on which devices trigger and where charge is stored. Some ESD devices may exhibit snap-back behavior, which rules out the use of ordinary circuit simulators. Instead, a specialized dynamic simulator is necessary to capture device triggering and the resulting voltage build-up afterwards.
of a device during a CDM discharge event
The metal structures of the involved nets do not look or act like simple lumped loads. Supply nets are often made up of wide metal and have complex current flow. This makes the methods used for extraction and simulation critical for obtaining accurate results.
Magwel has added a CDM simulation and verification tool to its ESD suite, which previously addressed HBM. Their successful HBM tool, called ESDi, has given them years of experience dealing with the fundamental issues of usability, performance and quality of results. Magwel is known for its highly accurate solver based extraction engine. Their special purpose simulation engines are also a key technology that enabled the development of their CDM offering, CDMi.
CDM protection is often used on large designs, to accommodate this Magwel R&D has rolled out a number of performance enhancements that offer much higher throughput. CDMi also takes advantage of parallel processing to ensure better runtimes. Error reporting that avoids an overload of false errors and debugging play a vital role in overall productivity, so Magwel has used its experience in this area to provide easy to use reporting and a cross-linked layout and field view capability that helps users identify the source of design issues.
Because of its unique solver based technology and their extensive experience in the ESD field, Magwel is well positioned to provide an effective solution for CDM protection network simulation and verification. With the rollout of the CDMi product and the level of interest it has garnered, it seems that Magwel is on the right track. The Magwel website has more information on CDMi and is well worth looking over.
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com