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Webinar on Transient Simulation of Power Transistors in Converter Circuits

Webinar on Transient Simulation of Power Transistors in Converter Circuits
by Tom Simon on 04-13-2020 at 6:00 am

Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency for wall-power operated circuits. One large consideration is that PowerMOS devices themselves do not operate as ideal devices. Performing circuit analysis at the device pins leaves out important information about what is happening inside these devices.

PTM TR high side low side currents

PowerMOS devices are really an assembly of large numbers of parallel intrinsic devices with a complex and distributed structure. As such, switching does not occur simultaneously across all the intrinsic devices. In converter circuits PowerMOS RC delays can affect Vgs over time at the gate contacts in low and high side transistors. Previously it has been difficult to run full circuit simulations that take this into consideration. Fine grain extraction of gate, source and drain interconnect is difficult for traditional circuit level extractors. Designers have struggled with this lack of visibility up until now.

Magwel offers a tool specifically targeted at realizing comprehensive and accurate simulation of converter circuits, including the complex internals of PowerMOS devices. Magwel’s PTM-TR does several unique things to provide transparency into the detailed switching behavior of PowerMOS devices. PTM-TR uses a solver-based extractor to correctly and accurately determine parasitics for the internal metallization within PowerMOS devices. The gate regions are divided up according to user set parameters and the intrinsic device model is applied to create a simulation view of the device that incorporates its full internal structure. This model is known as a Fast3D model and is used by PTM-TR with Cadence Spectre® to co-simulate dynamic gate switching behavior at each time step of circuit operation.

Because the Fast3D model is used in conjunction with Spectre circuit simulation, it can be used with test benches, or to perform any desired simulation, such as corner analysis. PTM-TR comes with the additional benefit of showing graphically a field view of the device internals at each time step. During early switching with only small sections of the device turned on higher than expected current densities are possible – leading to EM and thermal issues. With PTM-TR designers can modify and test PowerMOS devices to achieve optimal performance and reliability.

PTM TR header

To learn more and see how Magwel’s PTM-TR helps engineers optimize switching performance in converter circuits, sign up for the free webinar replay. Magwel Application Engineer Allan Laser will present an overview of the tool and then go through a demo that shows the simulation results and detailed insight into internal device operation during transient operation.


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