CadenceTECHTALK: Electrothermal co-simulation: Improve Hot Signoff Accuracy

CadenceTECHTALK: Electrothermal co-simulation: Improve Hot Signoff Accuracy
by Admin on 06-02-2022 at 12:00 am

Conference Date: June 02, 2022

Meeting time: 14:00 – 15:00 (Beijing time)

Traditional thermal simulation software often focuses on the heating of the device itself, and is not very friendly to the processing of circuit Joule heat. However, for some scenarios with high power consumption and high current, the influence

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Unlock first-time-right complex photonic integrated circuits

Unlock first-time-right complex photonic integrated circuits
by Raha Vafaei on 06-01-2022 at 10:00 am

EPDA overview

The capacity and energy efficiency challenges from the growing appetite for high-speed data along with advanced applications such as LIDAR and quantum computing are driving demand for increasingly large-scale photonic integrated circuits (PIC). With an ever-increasing number of components on a single photonic chip, manual… Read More


Aldec Adds Simulation Acceleration for Microchip FPGAs

Aldec Adds Simulation Acceleration for Microchip FPGAs
by Tom Simon on 11-10-2020 at 10:00 am

Simulation Acceleration

Despite the fact that FPGA based systems make it easy to add ‘hardware in the loop’ for verification, the benefits of HDL and gate level simulation are critical for finding and eliminating issues and bugs. The problem is that software simulators can require enormous amounts of time to run full simulations over sufficient time intervals… Read More


Webinar on Transient Simulation of Power Transistors in Converter Circuits

Webinar on Transient Simulation of Power Transistors in Converter Circuits
by Tom Simon on 04-13-2020 at 6:00 am

PTM TR high side low side currents 300x182 1

Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency… Read More


Aldec Swings for the Fences

Aldec Swings for the Fences
by Bernard Murphy on 03-17-2017 at 7:00 am

In today’s fast-moving technology markets, companies who are prepared to step up to opportunity can break out of traditional bounds to become players in bigger and fast-growing markets. It looks to me like Aldec is putting itself on that path. They have announced an end-to-end hardware/software co-verification solution… Read More


Striving for one code base in accelerated testbenches

Striving for one code base in accelerated testbenches
by Don Dingee on 08-26-2016 at 4:00 pm

Teams buy HDL simulation for best bang for the buck. Teams buy hardware emulation for the speed. We’ve talked previously about SCE-MI transactors as a standardized vehicle to connect the two approaches to get the benefits of both in an accelerated testbench – what else should be accounted for?… Read More


Aldec extends FPGA and ASIC flows at DAC

Aldec extends FPGA and ASIC flows at DAC
by Don Dingee on 05-20-2016 at 4:00 pm

Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same. … Read More


Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More


Simulating to a fault in automotive and more

Simulating to a fault in automotive and more
by Don Dingee on 08-30-2015 at 12:00 pm

We’re putting the finishing touches on Chapter 9 of our upcoming book on ARM processors in mobile, this chapter looking at the evolution of Qualcomm. One of the things that made Qualcomm go was their innovative use of digital simulation. First, simulation proved out the Viterbi decoder (which Viterbi wasn’t convinced had a lot … Read More


SystemC Co-Simulation of NoCs and IP Blocks

SystemC Co-Simulation of NoCs and IP Blocks
by Paul McLellan on 03-19-2015 at 7:00 am

Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.

The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously … Read More