Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same.
It shouldn’t be a surprise – after all, several of Aldec’s product families are designed for FPGA-based prototyping of SoCs. This is more of a question of the type of customer that Aldec has been working with over their 30-year plus history, and the state of many higher-priced EDA tools in general. By declaring its tool suite ready for ASIC verification tasks, Aldec is taking its competence to new places.
Those new places are most likely firms entering the chip design realm recently, or maybe even for the first time, and probably without massive sums of money to invest in EDA tools. This is a developing trend we’ve been reporting on for a while. A startup or a firm with domain expertise prototypes their idea in software on a merchant chip, but decides to customize silicon to maximize their product differentiation moving to production.
There is also the advantage of a cultural match. Nimble firms tend to want to partner up with other nimble firms. That’s not to say a bigger firm can’t service a smaller customer well, or a smaller supplier can’t handle a larger customer – but often, the fit between firms of roughly equivalent organizational “power” is better.
I’m sure Aldec would say their verification spectrum is ready for almost any job in ASICs, and from a technology standpoint that is probably true. Realistically speaking however, big firms pursuing big ASIC designs probably already have big EDA tools in house. This strategy is targeting primarily the small-to-medium fabless customer, perhaps one already familiar with some of the Aldec tools.
Aldec’s strengths are in a managed requirements environment, especially in critical-systems applications such as automotive, industrial, and mil/aero. Spec-TRACER is an essential piece to providing traceability, and ALINT-PRO can quickly automate RTL code reviews for industry-standards such as DO-254, STARC, and RMM, and provide advanced clock-domain-crossing (CDC) analysis. These front end tasks in the flow can have a huge payoff in reducing design errors that cause chip respins.
The back-end of the flow is the heart of design verification. Both the Riviera-PRO simulator and the HES-7 platform are designed to shake designs and uncover issues. HES-7 adds the capability to provide co-simulation with hardware acceleration, allowing more verification tests to be run in less time. It’s worth noting verification results are often only as good as the set of constraints used in the testbench – the Aldec suite uses a common set of constraints that move across the flow from beginning to end. Aldec also offers verification IP to speed up testbench construction.
Aldec says this is an “extension” of their spectrum of tools. On day one, the tools are probably exactly the same as what they’ve been selling – there is no new product being announced here. What has changed is how this Verification Spectrum of tools will evolve cooperatively with a new set of ASIC customers added to the mix. Aldec’s model is incremental releases, based on improvements designed to resolve customer issues and incorporate new ideas gained from actual customer usage.
For more on the Aldec ASIC Verification Spectrum and their extended focus on both ASIC and FPGA designs, CEO Dr. Stanley Hyduke has personally penned a blog:
Aldec also has a strong presence upcoming at DAC 2016 in Austin, with 10 technical sessions available for one-on-one 45 minute consultations via registration:
Aldec ASIC Verification Spectrum | DAC 2016, June 6-8, Austin TX | Booth #619
It’s a big step, one that I think companies looking for an experienced yet nimble ASIC partner will welcome.