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WIKI Multi FPGA Design Partitioning 800x100
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A Brief History of Aldec

A Brief History of Aldec
by Daniel Payne on 10-20-2012 at 5:31 pm

Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains a global network of regional offices and is the only EDA company to have Corporate Headquarters located in Nevada.


In the mid 1980’s another DOS-based tool called OrCAD was used for PCB schematic and layout, a good complement to SUSIE for simulation.

Microsoft Windows became a popular Operating System and Aldec introduced support in 1992 for Windows with the Active-CAD tools for schematic capture and gate level simulation.

FPGA vendor Xilinx offered a version of Active-CAD named Foundation starting in 1996 that worked only on Xilinx designs.

Hardware Description Languages (HDL) like VHDL and Verilog became popular as a more productive methodology than gate-level design for digital logic. Aldec added VHDL support in 1997 with the Active-VHDL product, then Verilog support with the Active-HDL product name. This product used graphical entry for an HDL-based design flow.

For the first 15 years Aldec products ran on Microsoft operating systems, then in 2000 two new platforms were added: Solaris and Linux.

The next year in 2001 the first hardware accelerator for HDL simulation was added, called the HES Platform(Hardware Emulation System).

Active-HDL serves the CPLD and mid-level complexity FPGA devices, while Riviera-PRO is for high-end FPGA design plus ASICs and debuted in 2003, also supporting mixed language support and assertion-based verification (OpenVera, PSL and SystemVerilog).

HDL languages extended into higher levels of abstraction, so support for SystemVerilog and SystemC were added in 2004.

For the military and aerospace markets a new compliance tool set called DO254-CTS was released for at-speed FPGA level in-target testing system for Levels A and B of DO-254 designs.

A new design rule and linting tool called ALINT launched in 2008 and analyzes Verilog and VHDL source code.

In 2010 the popular Active-HDL simulator was embedded into the Altium Designer tool.

Multiple verification standards arose, so in 2011 Aldec delivered support for: UVM 1.0, OVM 2.1.2 and VMM 1.1.1a.

New for 2012 is the HES-7 system for FPGA prototyping with a capacity of 4 to 96 million gates.

Summary
Today, Aldec EDA tools are used to design, simulate and verify FPGA, ASIC, SoC and embedded system designs. There are over 35,000 users of Aldec tools with distribution in over 43 countries. The biggest users of Aldec tools are FPGA designers, and Aldec has been granted six technology patents.

Aldec remains one of the few privately-held EDA companies with a 28 year history, while in that same time period the EDA industry has seen literally hundreds of smaller companies get acquired by larger ones.


Riviera-PRO


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