DAC 2025

DAC 2025
by Admin on 05-12-2025 at 5:52 pm

About DAC

DAC is recognized as the global event for chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical… Read More


Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli

Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli
by Daniel Nenni on 05-09-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is once again joined by Anna Fontanelli, founder and CEO of MZ Technologies. In this discussion, more details of the challenges presented by advanced packaging and multi-die design are explored. Anna provides details of what’s involved in architectural … Read More


Webinar: Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author

Webinar: Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author
by Admin on 05-08-2025 at 12:23 am

Wednesday, May 28 – 8:00 AM Pacific

Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs.

In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with

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Webinar: Solving the Semiconductor Verification Crisis: From Problem to Productivity

Webinar: Solving the Semiconductor Verification Crisis: From Problem to Productivity
by Admin on 05-08-2025 at 12:21 am

Wednesday, May 21 – 8:00 AM Pacific

The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.

This challenge is compounded by demands for Enhanced security, Reduced power

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Webinar: Intel Presents: Modern EDA Solutions for Scalable Heterogeneous Systems

Webinar: Intel Presents: Modern EDA Solutions for Scalable Heterogeneous Systems
by Admin on 05-01-2025 at 3:18 pm

Featured Speakers:

  • Vivek Rajan, Sr. Principal Engineer, Intel
  • Amlendu Choubey, Sr. Director, Product Management, Synopsys

Why You Should Attend:

Rapidly emerging new workloads and disruptive architectures have highlighted the importance of advanced packaging and 3DIC technologies. The scaling of Moore’s Law has pushed… Read More


Webinar: Using Veloce PCD to implement an Arm CSS with confidence

Webinar: Using Veloce PCD to implement an Arm CSS with confidence
by Admin on 04-22-2025 at 10:09 am

Software Defines Everything
For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification.

What is the Arm

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Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 04-09-2025 at 2:36 am

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Webinar: Master RF Signals: New Compact Solutions

Webinar: Master RF Signals: New Compact Solutions
by Admin on 03-26-2025 at 12:22 pm

About this event

Accurate, precise, and fast RF / μW analysis made simple.

Be among the first to explore our newest and most extensive collection of compact signal generators and source analyzers. Experience live product demos and gain insights into the unique features of each product, including:

• Ultra-low phase noise

• Signal

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Webinar: Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems

Webinar: Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems
by Admin on 03-24-2025 at 7:57 am

An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end RISC-V debug and trace solution consisting of embedded IPs and software that integrate with industry-standard tools.

We will… Read More