Webinar: New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Webinar: New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
by Admin on 02-26-2024 at 7:58 pm

About

Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains,Read More


Luc Burgun: EDA CEO, Now French Startup Investor

Luc Burgun: EDA CEO, Now French Startup Investor
by Lauro Rizzatti on 01-22-2024 at 6:00 am

Luc Burgun

When we last saw Luc Burgun’s name in the semiconductor industry, he was CEO and co-founder of EVE (Emulation and Verification Engineering), creator of the ZeBu (Zero Bugs) hardware emulator. EVE was acquired by Synopsys in 2012.

After the acquisition, Luc moved out of EDA and became an investor. Join me as I catch up with Luc and … Read More


Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
by Admin on 01-08-2024 at 2:00 pm

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly

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Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management

Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management
by Admin on 01-05-2024 at 4:33 pm

In a world where the chiplet market is projected to soar to $50.5 billion in revenue by 2024, staying ahead of the game is crucial. This monumental shift in the IC design ecosystem necessitates a forward-thinking approach to navigate the sea of data and intricate Intellectual Properties (IPs) securely.

That’s why Keysight… Read More


Preventing SOC Schedule Delays Using the Cloud

Preventing SOC Schedule Delays Using the Cloud
by Ronen Laviv on 12-25-2023 at 6:00 am

compute peaks 1

In my previous article, we touched on ways to pull in the schedule. This time I’d like to analyze how peak usage affects project timeline and cost. The above graph is based on real pattern taken from one development week in Annapurna Labs 5nm Graviton.

The Graph shows the number of variable servers per hour per day. There’s a baseline… Read More


2024 Signal & Power Integrity (SIPI) SIG Event

2024 Signal & Power Integrity (SIPI) SIG Event
by Admin on 12-18-2023 at 7:56 pm

What is SIPI SIG?

The Synopsys SIPI SIG Event is for Synopsys customers to hear the latest advances and solutions in signal and power integrity from customers and partners. This event provides the opportunity for networking and  discussion with fellow SIPI engineers to increase awareness of signal and power integrity issues

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Do you have Time to Pull in your Tapeout Schedule?

Do you have Time to Pull in your Tapeout Schedule?
by Ronen Laviv on 12-06-2023 at 10:00 am

schedule pullin

So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.

You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise… Read More


Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP
by Admin on 11-28-2023 at 4:42 pm

Summary

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging

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