In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.
During design implementation, varying degrees of constraining may be applied on the Reset signal. For example, designer may impose some multicycle paths (MCP) constraint in order to avoid unneeded timing optimization on the reset logic (although check for slew violation is still necessary). In this article we will discuss Reset mechanism and RDC (Reset Domain Crossings).
Just like the notion of hard- or soft-reboot in system bringup, we could first categorize this initialization step into hard/soft-reset as captured in figure 1.
In synchronous designs, asynchronous reset de-assertion operation causes metastability issue and unpredictable values in the memory elements. This increases risk of not having a stable design initialization. The snapshot in figure 2 illustrates the issue, in which the reset signal de-asserts during the active clock edge change –causing metastability issues as well as randomly initialized register values. To avoid a non-determinism, synchronization at reset deassertion is needed.
Synchronous and Asynchronous Reset
Let’s probe into the flip-flop element which sits in the center of this phenomenon, In the standard cell library, this storage element or register may come in two flavors, i.e, with reset and no-reset option. On the other hand, in the design RTL codes, registers may be pre-instantiated or left to be inferred during logic synthesis, depending on whether logic designer would like to impose control on the type of registers used. If inferred, logic synthesis will also infer reset implementation and select registers from the library with the corresponding set/reset configuration.
In the FPGA design, a slice may contain cluster of registers sharing a set of control signals such as clock, enable and reset related. Frequent endorsement of using a non-resettable register in FPGA design is stemmed from better device utilization in both Shift Register LUTs (SRL) and Block RAM (BRAM), although care should be given in initializing registers to known values during functional simulation as registers with undefined “X” states are very common occurences here.
Comparing two types of reset implementation, each comes with advantages and disadvantages.
Unlike ASICs, FPGA designs implement the Power-on-Reset function. It initiates program load into the bitstream and configures the LUT’s. The bitstream contains the initial values for every register and RAM bit in the device. Registers are initialized throughout the configuration process and the Global Set Reset (GSR) signal keeps the device in non-operational mode until the end of configuration stage.
Reset Synchronization Techniques
Since reset signal is external to a device and asychronous, it needs to be synchronized. The conversion and synchronization of external-to-device to internal-to-device reset signal can be achieved through multi-stage registers. A minimum of two clock cycles is required to ensure minimum reset pulse-width is met. However, depending on the type of registers (i.e, non-resettable) used, the reset synchronizer could require as much as ten clock cycles. It is recommended that any reset de-assertion should be done only upon stable clock and during its active operation. For example in some subsystems containing finite state machines or counters, all registers must come out of reset on the same clock edge to prevent illegal state transition.
Similar to the solution in Clock Domain Crossing (CDC), NDFF synchronizer can also be utilized as synchronizer across two clock domains. Since each domain has varying minimum pulsewidth requirement, a pulse stretcher can be inserted prior to the synchronizer to ascertain that minimum pulsewidth is met. In FPGA, glitch prevention may be warranted due to non-resettable registers being used. Initializing these registers to similar values of the external asynchronous reset signal should avoid possible reset glitches.
FPGA resources such as SRL and BRAM contain non-resettable registers and may introduce non-determinism as the GSR net can release different storage elements in different clock-cycles. This in turn triggers a chain reaction causing some registers to “wake-up” one or more clock cycles earlier than the others. Coupled with any presence of sequential loop-back condition, this may corrupt the initialization values and lead design into an unpredictable state.
The selection of non-resettable register is also to accommodate synthesis optimization techniques commonly seen in Intel’s devices, such as register retiming, pipelining or other register related netlist modifications. Register-specific optimizations are done only in the absence of an asynchronous reset. For list of design practices that could help eliminate non-determinism, refer to this.
In design with multiple reset signals targeting different sections of the system, RDC could occur. These signals introduce asynchronoous reset assertion events in each reset domain, which may lead to metastability and unpredictable design initialization (see figure 3a). The reset operation frequency also increase susceptibility to the RDC effect, and on the other hand, a proper reset ordering sequence should minimize its occurrences. Linting tools such asAldec’s ALINT-PRO™ help designer to identify RDC and other aspects of reset domains. It helps generate design assertions to confirm proper reset sequences are done in the design.
RDC synchronization methods includes isolating the receiving domain register from the source domain register. An enable such as “iso_en” is asserted prior to the assertion of “rst1”. The receiving registers holds its value during an asynchronously set FF data change as seen in figure 3b. Through linting step, such isolation cells used in RDC prevention can be identified and verification code can be generated to ensure correct operation of these “iso_en” signals relative to signal assertions. For discussion of other technique, refer to this.
Despite fewer occurrences compared with CDC, RDC has been getting more attention especially for heterogeneous designs with complex reset strategies and segregated regions needing frequent reset sequences. Preventing and fixing such condition can be addressed through the use of both Linting tools and subsequent functional verification.
For info on Aldec’s ALINT-PRO™, please checkhere,
For Aldec’s white-paper on RDC, please find ithere.