Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence

Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence
by Daniel Nenni on 06-11-2026 at 6:00 am

FPGA Prototyping Beyond RTL Fit Building Useful Pre Silicon Evidence

As semiconductor designs continue to grow in complexity, FPGA prototyping has become an essential component of modern pre-silicon validation strategies. While FPGA capacity and gate-count equivalence often dominate discussions around prototyping platforms, the true value of an FPGA prototype lies elsewhere: its ability… Read More


RDC – A Cousin To CDC

RDC – A Cousin To CDC
by Alex Tan on 04-18-2018 at 12:00 pm

In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying degrees of… Read More