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WIKI Multi FPGA Design Partitioning 800x100
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Webinar Replay – Insight into Creating a Common Testbench

Webinar Replay – Insight into Creating a Common Testbench
by Tom Simon on 06-04-2020 at 6:00 am

Common Tesbanch

These days the verification process starts right when the design process begins, and it keeps going well past the end of the design phase. Simulation is used extensively at every stage of design and can go a long way to help validate a design. However, for many types of designs, especially those that process complex data streams, … Read More


Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
by Daniel Nenni on 03-09-2020 at 6:00 am

Aldec Webinar SemiWiki

Before starting your next FPGA Prototyping Project you should catch the next SemiWiki webinar – “Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards”, in partnership with Aldec.

A significant portion of my  30+ years in the EDA industry has revolved around design verification with some form of FPGA … Read More


Enhancing Early Static FSM

Enhancing Early Static FSM
by Alex Tan on 08-08-2018 at 12:00 pm

Finite state machines (FSMs) are widely adopted as part of reactive systems to capture their dynamic behaviors using a limited number of modes or states that usually change according to the applied circumstances. Some terminologies are frequently used to describe the FSM characteristics: state, transition, condition and … Read More


RAL, Lint and VHDL-2018

RAL, Lint and VHDL-2018
by Alex Tan on 06-11-2018 at 12:00 pm

Functional verification is a very effort intensive and heuristic process which aims at confirming that system functionalities are meeting the given specifications. While pushing cycle-time improvement on the back-end part of this process is closely tied to the compute-box selection (CPU speed, memory capacity, parallelism… Read More


RDC – A Cousin To CDC

RDC – A Cousin To CDC
by Alex Tan on 04-18-2018 at 12:00 pm

In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying degrees of… Read More


Clock Domain Crossing in FPGA

Clock Domain Crossing in FPGA
by Alex Tan on 03-12-2018 at 12:00 pm

Clock Domain Crossing (CDC) is a common occurrence in a multiple clock design. In the FPGA space, the number of interacting asynchronous clock domains has increased dramatically. It is normal to have not hundreds, but over a thousand clock domains interactions. Let’s assess why CDC is a lingering issue, what its impact and the … Read More


Conflating ISO 26262 and DO-254

Conflating ISO 26262 and DO-254
by Bernard Murphy on 01-30-2018 at 7:00 am

If you’re in the ASIC business, by now you should have a rough understanding of ISO 26262, the safety standard for automotive electronics. You may be less familiar with DO-254 which has somewhat similar intent for airborne electronics. Unless, that is, you design with FPGAs in which case your familiarity may be the other way around… Read More


Webinar: ISO 26262 and DO-254: Achieving Compliance to Both

Webinar: ISO 26262 and DO-254: Achieving Compliance to Both
by Bernard Murphy on 01-11-2018 at 7:00 am

It’s near-impossible to read anything today about electronic design for cars without running into the ISO 26262 standard. If you design airborne electronic hardware, you’re likely very familiar with the DO-254 standard. But what do you do if you want to design a product to serve both markets? It looks like aircraft makers are increasingly… Read More


Aldec and High-Performance Computing

Aldec and High-Performance Computing
by Bernard Murphy on 12-21-2017 at 7:00 am

Aldec continues to claim a bigger seat at the table, most recently in their attendance at SC17, the supercomputing conference hosted last month in Denver. I’m really not sure how to categorize Aldec now. EDA company seems to miss the mark by a wide margin. Prototyping company? Perhaps, though they have a much stronger focus on end-applications… Read More


The DIY Syndrome

The DIY Syndrome
by Bernard Murphy on 11-09-2017 at 7:00 am

When facing a new design objective, we check off all the established tools and flows we know we are going to need. For everything else, we default to an expectation that we will paper over the gaps with scripting, documentation and spreadsheets. And why not? When we don’t know what we will have to deal with, in documentation, scheduling,… Read More