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WIKI Multi FPGA Design Partitioning 800x100
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WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been adopting the Universal Verification Methodology in order to make their verification results more robust, in less time.

RISC-V continues to grow in importance as an open source, Instruction Set Architecture (ISA), and at the dac.com site there are some 3,110 search results for RISC-V. I just expect this trend to continue, because engineers often want to customize aspects of their SoC for a specific purpose or domain. A big question then arises on how do you actually verify a RISC-V project.

Google has created a SV/UVM based instruction generator for RISC-V processor verification, then posted it on GitHub. There have been some 765 commits, so this is an actively supported instruction generator.

There are many RISC-V core projects around the world to choose from, and Ibex is a small, 32-bit RISC-V core, also available on Github with 1,860 commits to date.

Using Riviera-PRO Aldec simulates the UVM testbench with the Google DV random instruction generator and Ibex RISC-V core.

UVM Testbench RISC-V
Source: https://ibex-core.readthedocs.io/en/latest/verification.html

In the testbench SV classes are blocks with rounded corners, while SV modules are shown as square corners, finally the code to be run is depicted in blue with folded corners.

Random commands come from the Google DV generator, and the testbench also has random interrupts during testing. The co-simulation flow has both an ISS and RTL loaded with test binaries, simulations are run, then the results are compared by a Python script. You can have the same verification experience if you assemble all of the pieces:

  • SystemVerilog simulator that supports UVM (i.e. Riviera-PRO)
  • Instruction Set Simulator (Spike or OVPsim)
  • RISC-V toolchain

Here’s the flow of tools and files used for verification:

RISC V tool flow

The second half of the webinar was showing an actual, live demo of this verification flow in action, running the makefiles, scripts, simulators and comparison on a Linux platform. Batch mode verification was shown first verifying the Ibex core, then GUI mode was run next, and in both cases there were zero mismatches between the ISS and Riviera-PRO simulator results.

The GUI for Riviera-PRO had multiple windows: Source code, Classes, Assertions, Messages. In the upper right is the Classes Window, showing instances and hierarchy, methods, properties, derived classes and base classes.

Riviera PRO

A very useful documentation feature was how a UVM graph could be auto-generated within Riviera-PRO, as it showed memory interface agents, one interrupt agent, connections, and then stepped into instances for more details to understand connectivity.

UVM graph

An assertions window showed all assertions in one place, without having to look at multiple files, while seeing any failures, passes, and the time when it last happened, quite useful for debugging.

Next, the waveform viewer was invoked after restarting simulation, and they added waveforms from the DUT.

waveform viewer

Finally, they showed the RTL code coverage after simulation had finished, then generated an HTML cumulative summary.

code coverage

Summary

RISC-V is one of the biggest topics of 2020 for the electronics industry, and the ecosystem continues to grow each day, but verification can be a burden. Aldec showed in this webinar how their SystemVerilog simulator along with other tools could be used in verifying a RISC-V core called Ibex.

I’ve included links to each open source tool on Github, so go explore on your own and save some verification time, instead of starting from scratch.

To watch the archived webinar, visit here.

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