WP_Term Object
(
    [term_id] => 21679
    [name] => Scientific Analog
    [slug] => scientific-analog
    [term_group] => 0
    [term_taxonomy_id] => 21679
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 1
    [filter] => raw
    [cat_ID] => 21679
    [category_count] => 1
    [category_description] => 
    [cat_name] => Scientific Analog
    [category_nicename] => scientific-analog
    [category_parent] => 157
    [is_post] => 
)
            
UCIe 800x100 banner
WP_Term Object
(
    [term_id] => 21679
    [name] => Scientific Analog
    [slug] => scientific-analog
    [term_group] => 0
    [term_taxonomy_id] => 21679
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 1
    [filter] => raw
    [cat_ID] => 21679
    [category_count] => 1
    [category_description] => 
    [cat_name] => Scientific Analog
    [category_nicename] => scientific-analog
    [category_parent] => 157
    [is_post] => 
)

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
by Daniel Nenni on 06-05-2023 at 6:00 am

UCIe image2

Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More