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WIKI Multi FPGA Design Partitioning 800x100
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Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC-V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two things to note:

  • The presenter, Alexander Gnusin, is truly a verification expert. Before joining Aldec in 2017, Alex did ASIC design and verification at Freescale (Motorola), IBM, IDT, Nortel, and Ericsson plus a 3 year R&D stint with Synopsys.
  • Aldec is one of the strongest private EDA companies which offers you depth of experience (36 years) and approachablilty, both are key ingredients when facing leading edge verification challenges.

Here is the abstract and agenda. Register now and get the replay, no problem at all. I hope to see you there!

Abstract:
The entire processor industry is currently going through a paradigm shift – new generations of domain-specific proprietary processor cores based on the open-source RISC-V ISA are now being developed by various industry-leading semiconductor companies. Additionally, open-source RISC-V processor cores such as SweRV, Ibex and Pulp are now available, and they are actively being developed in various open-source Github communities.

Static verification or linting is a standard part of the tool flow for any processor-based designs to help engineers develop highly robust code in both IP and SoC levels. Static linting based on industry-best practice coding standards are critical in ensuring best-practice coding styles, efficient synthesis and timing closure, avoid simulation-to-synthesis mismatches, and proper usage of SystemVerilog constructs and data types. In this presentation, we will demonstrate how to statically verify RISC-V IP designs with the new ALINT-PRO RISC-V ruleset.

Agenda:

  • Current RISC-V design verification flow : the Overview
  • Advanced Linting with ALINT-PRO RISC-V Rules Plugin
    • ALINT-PRO Lintong for IP designs
    •  RISC-V Plugin overview
  • Running Advanced Linting on RISC-V designs:
    • Live demo of RISC-V cores linting
    • Issues & violations Analysis
  • Summary
  • QnA

Presenter Bio:
Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods – LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

About ALINT-PRO
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.

About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com


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