Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?
A Xilinx Zynq is a wonderful thing, especially for many IoT designs. Zynq provides a solid way to implement decimation, preprocessing high-speed incoming data using programmable logic, then performing software-based operations on a lower-rate stream. The approach fits embedded vision, software-defined radio, radar and lidar, multiprotocol IoT gateways, real-time analytics, and more applications.
There is no shortage of merchant boards with a Xilinx Zynq on board. Low-end parts are found on maker-class modules, while higher performance parts are showing up in more robust embedded form factors, usually with some form of daughterboard expansion capability. Development for Zynq has two sides. The software side looks quite familiar – it’s the same as for any other ARM Cortex-A processor. On the hardware side, designers can grab the Xilinx Vivado Design Suite and with some knowledge of RTL, VHDL, or Verilog get rolling. Vivado handles synthesis and debug, and recently added basic simulation tools.
FPGA designers are very used to grabbing requirements, implementing a design, testing it, and iterating until it “works”. On the IoT, if the process stops there, the danger flag should go up. With the flow of critical data, any flaw in the FPGA design is just as big as a flaw in an SoC or any other hardware. Where no SoC designer worth their salt would think about skipping verification, FPGA designers often do. Why? Putting together a tool set for advanced verification and debug, well beyond the basic capabilities of Xilinx Vivado, takes effort.
When you see the headline that Aldec has announced a Zynq-based TySOM Embedded Development Kit, it might cause some wonder as to why an EDA company is getting into the embedded board business. Aldec has significant experience in FPGA-based prototyping hardware, so the hardware design itself isn’t a big stretch. What makes the Aldec entry very different is how it works with Vivado to solve the problem of advanced verification of Zynq designs for the IoT.
That’s right – it works with Vivado, it doesn’t replace it. Aldec Riviera-PRO integrates into Vivado as a TcL application, putting Aldec’s 30 plus years of verification experience to work. Riviera-PRO is a massive upgrade in simulation performance and support for more language constructs compared to the simulator in Vivado. It also extends debug capability with tracing, waveform, dataflow, finite state machine, and array plotting capability. By adding Aldec Riviera-PRO, more tests can be run against a Zynq design in far less time, increasing the confidence in an IoT application engine handling data that has to work.
The other piece of this is why Aldec chose to develop their own hardware – two boards, in fact. The TySOM-1 uses a mid-range XC7Z030 focuses on Zynq peripherals plus a Digilent Pmod-compatible header, while TySOM-2 moves to higher performance Zynq parts with two FMC HPC connectors to add daughtercard hardware easily. For example, Aldec has an FMC ADAS card with 5 camera socket modules, a lidar connector, and an ultrasonic sensor connector – the type of stuff needed for automotive and robotics. The design flexibility, especially of the TySOM-2 variant, blows away the maker modules and is on par with other embedded merchant boards.
Completing the kit is out-of-box support in Ubuntu Embedded Box reference designs. While Xilinx offers the PetaLinux tools to help get Linux up and running, the Aldec reference designs are already ported to the TySOM modules and contain support for IoT needs such as a USB webcam, a PmodGPS receiver, and more.
The combination of best-of-breed tools – Zynq, Vivado, Riviera-PRO, Ubuntu, and Aldec hardware – is what makes these kits intriguing for higher-end IoT designs, where designs must be optimized and verified. For more details on the Aldec TySOM Embedded Development Kits:
Exploring and optimizing programmable logic in high-performance IoT applications can be the difference between success and spectacular failure. Putting Riviera-PRO to work on verification for the FPGA side of the Zynq provides a huge advantage in creating robust testbenches and making sure an IoT design is thoroughly covered. The bundle puts design teams, especially those with less FPGA design experience (perhaps the majority of IoT designers who tend to come from software backgrounds), ahead in the ability to quickly differentiate a Zynq-based design.