CTO Interview with Taylor Barton of Certus Semiconductor

CTO Interview with Taylor Barton of Certus Semiconductor
by Daniel Nenni on 11-04-2026 at 12:00 pm

Smaller footprint, greater possibility

Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More


RISC-V Summit North America 2027

RISC-V Summit North America 2027
by Admin on 10-27-2026 at 10:43 pm

RISC-V Summit North America 2027 is taking place from February 16 to 18 at the Hyatt Regency, Embarcadero in San Francisco, California. February 16 is Member Day and the main conference will begin on February 17.

RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. SHD Group estimates

… Read More

Webinar: Testing Cars That Don’t Exist (Yet): Extending the Automotive Software Factory with Virtual ECUs

Webinar: Testing Cars That Don’t Exist (Yet): Extending the Automotive Software Factory with Virtual ECUs
by Admin on 09-17-2026 at 3:28 pm

Software factories have transformed automotive software development through automation, continuous integration, and rapid feedback cycles, yet achieving the same level of automation and continuous validation across the entire vehicle remains a major challenge. However, by creating complete virtual vehicles, engineering… Read More


Hot Chips 2026: Architectures for the Agentic Computing Era

Hot Chips 2026: Architectures for the Agentic Computing Era
by Daniel Nenni on 08-19-2026 at 2:00 pm

Hot Chips 2026 Agentrys Quadric SemiWiki

Hot Chips 2026, formally the thirty-eighth Symposium on High Performance Chips, arrives at Stanford’s Memorial Auditorium from August 23 through 25 with a program that captures a decisive shift in computer architecture. Peak arithmetic throughput remains important, but the conference is increasingly about system balance:… Read More


Industry’s First Certified Automotive Grade PUF for Software Defined Vehicles

Industry’s First Certified Automotive Grade PUF for Software Defined Vehicles
by Kalar Rajendiran on 07-30-2026 at 10:00 am

Automotive PUF Premium System Level Diagram

Software defined vehicles (SDVs) are transforming the automotive industry. Today’s vehicles are connected computing platforms that rely on advanced processors, artificial intelligence (AI), over the air (OTA) software updates, cloud services, and vehicle to everything (V2X) communications. Every electronic … Read More


The Architecture of Success: Why a Unified Semiconductor IP Strategy Is the Foundation of Modern SoC Design

The Architecture of Success: Why a Unified Semiconductor IP Strategy Is the Foundation of Modern SoC Design
by Kalar Rajendiran on 07-21-2026 at 10:00 am

Application Contexts That Span Markets

As architects push toward advanced nodes and increasingly demanding workloads, modern silicon design has entered an era of unprecedented complexity. A single design respin can cost millions of dollars and delay market entry. Against this backdrop, designs must be balanced for performance, bandwidth, power efficiency, security… Read More


See Defacto Technologies at DAC 2026

See Defacto Technologies at DAC 2026
by Daniel Nenni on 07-20-2026 at 2:00 pm

dac banner defacto

I have had the pleasure of working with Defacto Technologies for the past 10 years on SemiWiki and I am always impressed with their professionalism and ability to quickly address the challenges of complex SoC design.

From my perspective, Defacto’s technology is designed to improve productivity and design quality by enabling … Read More


Foundation IP for Intel 18A: Technical Overview and Why It Matters

Foundation IP for Intel 18A: Technical Overview and Why It Matters
by Daniel Nenni on 07-03-2026 at 6:00 am

Intel 18A Foundation IP Synopsys

Synopsys Foundation IP for Intel 18A is a portfolio of semiconductor building blocks designed to help system-on-chip developers build advanced chips with better power, performance, and area, often called PPA. The offering includes embedded memory compilers, standard-cell logic libraries, and input/output libraries for… Read More


Connecting the Dots: Why RISC-V System Design Is Entering a New Era

Connecting the Dots: Why RISC-V System Design Is Entering a New Era
by Kalar Rajendiran on 05-04-2026 at 10:00 am

Andes x Arteris Pre Verified and Silicon Proven SoC Integration

At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More