LIVE WEBINAR: Introduction to OpenCPI (US)

LIVE WEBINAR: Introduction to OpenCPI (US)
by Admin on 06-30-2022 at 11:00 am

Abstract:

The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies

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Advances in OSVVM’s Verification Data Structures (US)

Advances in OSVVM’s Verification Data Structures (US)
by Admin on 06-23-2022 at 11:00 am

Abstract:

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously

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Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
by Admin on 06-09-2022 at 11:00 am

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 9, 2022

11:00 AM – 12:00 PM (PDT)… Read More


LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
by Admin on 05-26-2022 at 11:00 am

Part 1: OSVVM – Leading Edge Verification for the VHDL Community (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, May 26, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

OSVVM is an advanced verification methodology that defines a VHDL verification framework,

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LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 4: Code, Functional and Specification Coverage (US)

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 4: Code, Functional and Specification Coverage (US)
by Admin on 05-19-2022 at 11:00 am

Espen Tallaksen, CEO of EmLogic

Thursday, May 19, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method

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FPGA Design/Verification: Randomization

FPGA Design/Verification: Randomization
by Admin on 05-12-2022 at 11:00 am

FPGA Design/Verification Best-Practices for Quality and Efficiency
Part 3: Randomization – The Why, When, What & How (US)

Time: 11:00 AM – 12:00 PM PDT

Abstract:

Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means

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LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency
by Admin on 05-05-2022 at 10:00 am

Part 2: FPGA Verification Architecture Optimization with UVVM (US)

Espen Tallaksen, CEO of EmLogic

Thursday, May 5, 2022

11:00 AM – 12:00 PM (PDT)

REGISTER HERE

Abstract:

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture

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LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency
by Admin on 04-28-2022 at 12:00 am

Abstract:

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be

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LIVE WEBINAR: Running CDC Analysis with Xilinx Parameterized Macros (US)

LIVE WEBINAR: Running CDC Analysis with Xilinx Parameterized Macros (US)
by Admin on 04-14-2022 at 12:00 am

Abstract:

Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably.

Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and

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3-Day DO-254 Practitioner’s Course

3-Day DO-254 Practitioner’s Course
by Admin on 09-15-2021 at 12:00 am

Course Synopsis:

Designed to provide a comprehensive understanding of DO-254 specification, objectives and requirements for airborne electronic hardware development, and teach efficient, well-proven and compliant methods to enable a faster, easier and more cost-effective path to FAA certification.

Day 1:  Understand… Read More