3-Day DO-254 Practitioner’s Course

3-Day DO-254 Practitioner’s Course
by Admin on 09-15-2021 at 12:00 am

Course Synopsis:

Designed to provide a comprehensive understanding of DO-254 specification, objectives and requirements for airborne electronic hardware development, and teach efficient, well-proven and compliant methods to enable a faster, easier and more cost-effective path to FAA certification.

Day 1:  Understand… Read More


Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU)

Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU)
by Admin on 03-25-2021 at 12:00 am

Time: 3:00 PM – 4:00 PM (CET)

Abstract:

The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based… Read More


Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US)

Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US)
by Admin on 03-18-2021 at 12:00 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation

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Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US)

Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US)
by Admin on 02-25-2021 at 12:00 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation… Read More


Functional Verification of Clock Domain Crossing Issues (US)

Functional Verification of Clock Domain Crossing Issues (US)
by Admin on 02-18-2021 at 12:00 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

ALINT-PRO provides powerful means for static analysis and validation of clock domain crossings(CDC). It extracts and validates clock trees, and clock domains, applying topological pattern-matching methods to validate the correctness of design structures on the clock domain boundaries.… Read More


Verifying PCIe 5.0 with PLDA, Avery and Aldec

Verifying PCIe 5.0 with PLDA, Avery and Aldec
by Bernard Murphy on 11-03-2020 at 6:00 am

little fish big fish min

Mike Gianfagna, a fellow SemiWiki blogger and a one-time colleague at Atrenta shared a useful piece of marketing advice. If your company is not the biggest fish in the pond and you want to appear more significant, team up with other companies to put on an event, say a webinar. Pick your partners so that you can jointly offer a larger,… Read More


How to Build PCIe Speed Adapters for In-Circuit SoC Emulation

How to Build PCIe Speed Adapters for In-Circuit SoC Emulation
by Daniel Nenni on 10-22-2020 at 11:00 am

Abstract:

Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs such as Xilinx Virtex UltraScale US440 and their adoption for emulation verification environments. One of the advantages of FPGA-based emulation systems is that it’s much more flexible than traditional processor-based… Read More


High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)

High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)
by Daniel Nenni on 10-15-2020 at 11:00 am

Abstract:

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More


Webinar Replay – Insight into Creating a Common Testbench

Webinar Replay – Insight into Creating a Common Testbench
by Tom Simon on 06-04-2020 at 6:00 am

Common Tesbanch

These days the verification process starts right when the design process begins, and it keeps going well past the end of the design phase. Simulation is used extensively at every stage of design and can go a long way to help validate a design. However, for many types of designs, especially those that process complex data streams, … Read More