LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)
Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 9, 2022
11:00 AM – 12:00 PM (PDT)… Read More
Espen Tallaksen, CEO of EmLogic
Thursday, May 19, 2022
11:00 AM – 12:00 PM (PDT)
Abstract:
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method
…
Read More
Part 2: FPGA Verification Architecture Optimization with UVVM (US)
Espen Tallaksen, CEO of EmLogic
Thursday, May 5, 2022
11:00 AM – 12:00 PM (PDT)
REGISTER HERE
Abstract:
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture
…
Read More
Course Synopsis:
Designed to provide a comprehensive understanding of DO-254 specification, objectives and requirements for airborne electronic hardware development, and teach efficient, well-proven and compliant methods to enable a faster, easier and more cost-effective path to FAA certification.
Day 1: Understand… Read More