aldec Archives - SemiWiki

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)
by Admin on 08-07-2023 at 4:49 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)
by Admin on 08-07-2023 at 4:48 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 3: Advanced Testbench for a Complex DUT (US)

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 3: Advanced Testbench for a Complex DUT (US)
by Admin on 04-24-2023 at 3:30 pm

Abstract:

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to … Read More

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 2: Advanced Testbench for a Simple DUT (US)

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 2: Advanced Testbench for a Simple DUT (US)
by Admin on 04-24-2023 at 3:22 pm

Abstract:

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 1: Basic Testbench for a Simple DUT (US)

LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 1: Basic Testbench for a Simple DUT (US)
by Admin on 04-24-2023 at 3:19 pm

Abstract:

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then

Webinar: The Power of Verilog’s PLI and VPI for FPGA Designs

Webinar: The Power of Verilog’s PLI and VPI for FPGA Designs
by Admin on 04-03-2023 at 3:29 pm

Abstract

The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending… Read More

Webinar: Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

Webinar: Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs
by Admin on 02-13-2023 at 3:07 pm

Summary

The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part of a robust verification process that includes advanced linting and … Read More