Philipp Wagner, Co-maintainer of cocotb and Hardware/Software Engineer at lowRISC
Abstract:
Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software engineering community has come up with
Sunil Sahoo, Corporate Applications Engineer
Thursday, October 20, 2022
11:00 AM – 12:00 PM (PDT)
Abstract:
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation,
Abstract:
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously
LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)
Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 9, 2022
11:00 AM – 12:00 PM (PDT)… Read More
Abstract:
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies
Part 1: OSVVM – Leading Edge Verification for the VHDL Community (US)
Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, May 26, 2022
11:00 AM – 12:00 PM (PDT)
Abstract:
OSVVM is an advanced verification methodology that defines a VHDL verification framework,
Espen Tallaksen, CEO of EmLogic
Thursday, May 19, 2022
11:00 AM – 12:00 PM (PDT)
Abstract:
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method
| FPGA Design/Verification Best-Practices for Quality and Efficiency Part 3: Randomization – The Why, When, What & How (US) Time: 11:00 AM – 12:00 PM PDT Abstract: Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means |
Part 2: FPGA Verification Architecture Optimization with UVVM (US)
Espen Tallaksen, CEO of EmLogic
Thursday, May 5, 2022
11:00 AM – 12:00 PM (PDT)
Abstract:
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture
Abstract:
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably.
Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and
