Continuous, incremental improvement based on customer feedback and insight from researchers is a pillar of the Aldec EDA strategy. Within the last two weeks, two of the Aldec product lines – Riviera-PRO, and ALINT-PRO-CDC – have seen new version releases. Here’s a quick look at some of the highlights of both.
Riviera-PRO 2015.06 released to the public on July 30. The major enhancement in this release of Aldec’s mixed-language simulation and verification tool is better coverage analysis capability. For SystemVerilog users, condition coverage has been introduced, gathering coverage information on expressions inside if statements and the conditional ?: operator. The option to collect condition coverage is easily enabled from a command line or the GUI interface. For VHDL users, path coverage has been introduced, with similar control via command line.
The results of coverage analysis are displayed in HTML reports, extracted from merged ACDB files. Reports show the number of hits on a conditional expression, and mousing over the hit count reveals a tool-tip that shows which test names covered the bin. Further information is shown in a test details table of the ACDB report.
Other features have been added, such as a UVM configuration window for debugging. This shows resources available in the UVM configuration database, tracking user-defined information and UVM scope. Keeping pace with open source releases, the OpenSSL library bundled with Riviera-PRO has been updated to version 1.0.2a, and the OSVVM library has been updated to version 2015.03. Also to be appreciated is a streamlined installation process, using an upgraded version of the setup program which reduces installation time by half.
ALINT-PRO-CDC 2015.08 released to the public on August 10, and is the subject of a live webinar with Aldec product manager Pavel Leshtaiev coming up on August 13. This clock domain crossing analysis tool performs in-depth automated analysis using both static and dynamic methods. Ten new rules have been added to the rules plug-in, enhancing the ability to locate CDCs and reducing the chance of random logic being incorrectly identified as a clock.
Static checks have received new visual highlighting in schematics. For example, all nets in a particular clock domain can be highlighted with a color for easy observation. Convergence through combinational logic is also highlighted with color.
A big part of ALINT-PRO-CDC is not just detection of CDCs, but also verification of synchronizer constructs that mitigate them. Assertions and coverage extensions help with EN-based and handshake synchronizers, and metastability emulation is generated for reset synchronizers. Also, the concept of virtual clocks has been added; for example, a delay can be specified on an input or output port.
A major new feature is the format of the automatically generated testbench. Three formats are now supported: SystemVerilog, VHDL with PSL for assertions and coverage, and pure VHDL with assertions but no coverage. Users can control which of these formats is created.
As always from Aldec, following those links leads to a What’s New presentation and a complete set of detailed release notes.
Again, many of these enhancements come from requests by actual users in these tools working on real-world designs. Often the addition of an individual feature might seem minor, but the constant sweeping by Aldec development teams with these enhancements adds up to significant productivity improvements, and keeps these tools on the leading edge.Share this post via: