Clock Domain Crossing in FPGA

Clock Domain Crossing in FPGA
by Alex Tan on 03-12-2018 at 12:00 pm

Clock Domain Crossing (CDC) is a common occurrence in a multiple clock design. In the FPGA space, the number of interacting asynchronous clock domains has increased dramatically. It is normal to have not hundreds, but over a thousand clock domains interactions. Let’s assess why CDC is a lingering issue, what its impact and the … Read More


Aldec updates two EDA product lines

Aldec updates two EDA product lines
by Don Dingee on 08-12-2015 at 4:00 pm

Continuous, incremental improvement based on customer feedback and insight from researchers is a pillar of the Aldec EDA strategy. Within the last two weeks, two of the Aldec product lines – Riviera-PRO, and ALINT-PRO-CDC – have seen new version releases. Here’s a quick look at some of the highlights of both.

Riviera-PRO 2015.06… Read More


Synchronizer Optimization 101

Synchronizer Optimization 101
by Daniel Nenni on 02-22-2015 at 9:00 pm

A webinar presented Last week introduced two free aids to evaluating synchronizer Mean Time Between Failures (MTBF). The first, MetaACE LTD, is used to characterize the intrinsic parameters needed to calculate MTBF (tau and Tw). This limited version of MetaACE supports up to 250 circuit nodes, which is enough for a typical C-only-extracted… Read More


Writing the unwritten rules with ALINT-PRO-CDC

Writing the unwritten rules with ALINT-PRO-CDC
by Don Dingee on 02-09-2015 at 11:30 am

EDA verification tools generally do a great job of analyzing the written rules in digital design. Clock domain crossings (CDCs) are more like those unwritten rules in baseball; whether or not you have a problem remains indefinite until later, when retaliation can come swiftly out of nowhere.

Rarely as overt or dramatic as a bench-clearing… Read More


A Public Synchronizer

A Public Synchronizer
by Jerry Cox on 02-09-2015 at 7:00 am

You might ask yourself “Why would anyone want to have a public synchronizer available to download?” Usually designers just grab a flip-flop from his or her company’s or a standard cell vendor’s library. However, are these handy solutions the best course of action today? Current SoC designs have numerous clock domains providing… Read More


Measuring Metastability

Measuring Metastability
by Jerry Cox on 01-24-2015 at 7:00 am

Measuring metastability is just 50 years old this year. In 1965 my colleague Tom Chaney took a sampling ‘scope picture of an ECL flip-flop going metastable. S. Lubkin had made mention of the phenomenon over a decade before that, but at that time most engineers were unaware of the phenomenon or did not believe it actually existed. … Read More


Dominating FPGA clock domains and CDCs

Dominating FPGA clock domains and CDCs
by Don Dingee on 09-26-2014 at 7:00 am

Multiple clock domains in FPGAs have simplified some aspects of designs, allowing effective partitioning of logic. As FPGA architectures get more flexible in how clock domains, regions, or networks are available, the probability of signals crossing clock domains has gone way up.… Read More


Metastability Starts With Standard Cells

Metastability Starts With Standard Cells
by Daniel Nenni on 07-24-2013 at 8:05 pm

Metastability is a critical SoC failure mode that occurs at the interface between clocked and clockless systems. It’s a risk that must be carefully managed as the industry moves to increasingly dense designs at 28nm and below. Blendics is an emerging technology company that I have been working with recently, their MetaACERead More


The never-ending quest to kill metastability

The never-ending quest to kill metastability
by Don Dingee on 05-28-2013 at 4:00 pm

The difficulty of an engineering problem can be gauged by two things:
1) The number of attempts to generate a solution.
2) The degree of hyperbole used to describe the effectiveness of the latest solution.

The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability… Read More