Synchronizer Optimization 101

Synchronizer Optimization 101
by Daniel Nenni on 02-22-2015 at 9:00 pm

A webinar presented Last week introduced two free aids to evaluating synchronizer Mean Time Between Failures (MTBF). The first, MetaACE LTD, is used to characterize the intrinsic parameters needed to calculate MTBF (tau and Tw). This limited version of MetaACE supports up to 250 circuit nodes, which is enough for a typical C-only-extracted synchronizer netlist. You will need the transistor model supplied by your foundry, in addition, but that is all that is required to get an approximate value for the MTBF at any process corner, value of supply voltage or junction temperature.

To calculate the MTBF of a synchronizer based on a fully extracted netlist will require the professional version ofMetaACE. This tool is typically used before tapeout, but the limited version is useful at an earlier point in the design cycle to compare different synchronizer designs. It can also be used to optimize a design for synchronizer service where clock-to-Q can be allowed to increase in order to minimize metastability resolving-time.

Another aid introduced during the webinar was A Public Synchronizer design that can serve as a benchmark to compare with a standard-cell flip-flop you may be planning to use. This Public Synchronizer is a straightforward master-slave circuit that includes a scan circuit for good testability. However, the layout of its regenerating transistors has been optimized for synchronizer service.

If you are contemplating solving a clock-domain-crossing issue with a synchronizer, it might be a good idea to take a look at the Blendics webinar to see if these free aids to design might be useful to you.

A UNIQUE APPROACH
In essence, we have focused our solution on how IP-Cores and other components communicate. Traditionally, IC components communicate synchronously via a global clock that controls each and every individual component and forces them to talk to each other in lock-step. So, we asked the question, how can we find a better way to support more robust communication requirements while not asking design teams to throw out existing IP or having to learn new approaches to designing IP?

OUR ANSWER
a globally asynchronous design methodology where we break the IC design into small independently operating IP-Cores and then re-connect each of the cores to each other, allowing each to communicate on its own timescale.

THE “AHA” MOMENT
It was 2004, and three of our founders were attending an international symposium they organized on Clockless Computing (Coordinating Billions of Transistors), at Washington University in St. Louis, Missouri. In the program, leaders in asynchronous computing reviewed future design challenges imposed on IC densities according to Moore’s Law.
We saw that work on asynchronous computing done decades earlier toward the goal of arbitrarily-large, discrete-component computer systems would be relevant again, this time at the microscopic scale. These older clockless techniques could be blended with modern clocked methods to solve the anticipated complexity and reliability challenges and thereby achieve continued Moore’s Law scalability. Bingo! we said to ourselves.

THE FORMATION OF BLENDICS

So, after much discussion and excitement, we determined that we could make a real difference. We brought together an astonishing group of mega-talented people who have each had a significant hand in some of the world’s most impactful technological innovations over the last 50 years, and in 2007, launched Blendics.

Our name “Blendics” can be deconstructed as: Blended Integrated Circuit Systems.