Measuring metastability is just 50 years old this year. In 1965 my colleague Tom Chaney took a sampling ‘scope picture of an ECL flip-flop going metastable. S. Lubkin had made mention of the phenomenon over a decade before that, but at that time most engineers were unaware of the phenomenon or did not believe it actually existed. Later many who saw the sampling ‘scope picture doubted the method’s validity. Subsequently, flip-flop output-voltage traces, patiently photographed by Tom in a darkened room, began to turn the tide. This lead to a paper that was rejected because one reviewer (perhaps and electrical engineer) saw a simple analog circuit that he felt was old and uninteresting and another reviewer (perhaps a computer scientist) said metastability could never occur so the paper should be rejected. Later in 1973 the classic Chaney and Molnar paper was accepted for publication in the IEEE Transaction on Computers.
Reliable measurement of metastability in synchronizers and arbiters has been hard to realize. Many subtle problems deceive the unwary and adequate simulation tools and models became available only in the 1980s. Here is a list of several of the major problems:
- Measurements in silicon can only be made in circuits specially designed for that purpose. Simulation in advance of fabrication should be done for any other circuit and is preferable to avoid product re-spins.
- Shorting the metastable nodes, either in silicon or in simulation, seems painless, but actually yields erroneous results. This is because the method is only valid if the circuit behaves symmetrically. However, hardly any synchronizers really do.
- Most synchronizers today are master-slave designs and the recovery characteristics of the master and slave latches are usually quite different. This requires measurement of the characteristics of both latches and the calculation of an effective settling time-constant.
- The effective settling time-constant is a function of the clock waveform and duty-cycle.
- The load on the output of a synchronizer affects its behavior so care must be taken to include the subsequent circuit in simulations.
- The component stages in a multistage synchronizer interact with each other invalidating the simple concept of multiplying their failure probabilities.
- Beside clock domain crossings the potential for metastability hides in many surprising places: initialization logic, flip-flop reset signals, memory interfaces and analog input circuits.
Synchronizer designers need a tool for metastability analysis that overcomes these problems, has been proved in silicon and is easy to use. MetaACE from Blendics fits that need, but does not help with the collateral need for an educational tool that makes it easy for synchronizer designers, SoC engineers and engineering students to learn about metastability in its many manifestations.
To meet this educational need, Blendics is announcing MetaACE LTD, a version of MetaACE that limits the number of netlist nodes it can analyze to 250 or less. This node limitation does not otherwise narrow the functionality of the tool. MetaACE LTD is sufficient to handle most unextracted netlists and many netlists with capacitance-only extractions. Doing capacitance-only simulations also improves the run-time with only a small loss in accuracy. Other than the node limit, the two tools are the same and share GUIs and file formats.
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MetaACE LTD is available for free download. There will be a Webinardescribing its use on Wednesday 18 Feb 2015 at 11 AM PT. Also, a public synchronizer is soon to be available for download including an extracted netlist and transistor model. This public synchronizer was developed as a master’s thesis project at Southern Illinois University Edwardsville. It can provide a benchmark for comparison with your favorite synchronizer circuit and is a great way to try out MetaACE LTD.