You might ask yourself “Why would anyone want to have a public synchronizer available to download?” Usually designers just grab a flip-flop from his or her company’s or a standard cell vendor’s library. However, are these handy solutions the best course of action today? Current SoC designs have numerous clock domains providing many opportunities for metastability mischief at the crossings between these domains. Using handy solutions without fully understanding their reliability is dangerous for the design of safety-critical products
Modern flip-flop designs use high Vth transistors to reduce power while maintaining low clock-to-Q delay, but ignore synchronizer performance. Some firms have developed specialized synchronizer standard cells with high mean-time-between failures (MTBF). This measure of reliability depends on the synchronizer’s recovery time-constant tau and vulnerability window Tw. In safety-critical designs, synchronizer MTBF can be improved substantially by reducing tau at the expense of power and clock-to-Q delay. Such specialized designs provide a competitive advantage and are usually considered confidential IP that must be kept hidden.
Keeping the design and performance of these private synchronizers under wraps makes it impossible to compare their performance or establish benchmarks. Engineering students and researchers’ understanding of synchronizer subtleties is hindered.
To overcome these drawbacks our colleagues at Oracle and Southern Illinois University Edwardsville have developed a public synchronizer that provides many benefits:
- Engineers can use the public synchronizer’s extracted netlist to compare a synchronizer MTBF obtained with their in-house analysis tool against that obtained with MetaACE, a Blendics tool verified in silicon.
- Designers can layout the public synchronizer in their current process so that it serves as a benchmark for new designs.
- Researchers and engineers can use the public synchronizer to investigate the effect of changes in semiconductor processes (P), supply voltages (V), or junction temperatures (T) on MTBF and do this without exposing details of their private synchronizer design.
- Students can use the public synchronizer‘s extracted netlist and the associated FreePDK to study synchronizer design issues.
The above benefits sound useful so let’s look at the Public Synchronizer design. Two cascaded level-sensitive multiplexer-based latches, a master and a slave, were chosen as the basic design and for good testability a Level Sensitive Scan Design (LSSD) was also included. Although a synchronizer and a data flip-flop use this same circuit, the characteristics to be optimized are very different. Ian W. Jones of Oracle Labs, suggested a design based on a standard textbook circuit. George Engel and Sam Dunham, both at Southern Illinois University Edwardsville, optimized transistor sizing for synchronizer service and completed the layout.
This layout and fully extracted netlist were obtained using the FreePDK, a purposely non-manufacturable, Free Open-Access 45nm Process Design Kit and Standard Cell Library from North Carolina State University. The public synchronizer circuit occupies an area of 16 sq μm and possesses a t(CLK−Q) of 55ps. An analysis by the Blendics tool, MetaACE, gave a tau(eff) of 13ps and a Tw of 43fs when the synchronizer was operated from a 1.0 Volt supply. For clock and data rates of 1.5 GHz and a 50% duty cycle, the synchronizer MTBF is 1.6 x 10e6 years assuming 85% of a full clock period is available for synchronizer resolution. A two-stage synchronizer with the same clock rate, data rate and resolution-time assumption would have an MTBF of 5.5 x 10e37 years, a much more prudent value for a safety-critical application with a production volume of a million or more units.
Try the public synchronizer using your process. How does its MTBF compare to what you have been using? If you don’t have a convenient way to measure MTBF download MetaACE LTDand attend the Blendics webinar.