DVCon Taiwan 2026by Admin on 09-02-2026 at 11:05 pm
About DVCON
DVCon Taiwan is the premier conference for design and verification engineers, researchers, and managers in Taiwan’s semiconductor and EDA industries. Now in its third year, DVCon Taiwan 2026 continues its mission to bring together the local and international community to exchange ideas, explore the latest… Read More
Agentic artificial intelligence is likely to give the open-source electronic design automation market a meaningful boost. Its biggest contribution will not be the immediate replacement of established commercial platforms from Cadence, Synopsys, or Siemens. Instead, agentic AI can make open-source tools easier to use, … Read More
Featured Speakers:
- Madhumita Sanyal, Sr. Director of Technical Product Management, Synopsys
- Varun Agrawal, Director of Product Management, Synopsys
As SoC complexity climbs, traditional verification can’t keep pace — and system-level bugs surface late, when they’re hardest to fix. By pairing Hardware-Assisted… Read More
After speaking with dozens of semiconductor professionals at the Design Automation Conference in Long Beach about AI in the chip-design workflow, Claude emerged as the common denominator in every conversation. We’re still at the tip of the iceberg when it comes to using AI in the design flow. If management is pushing your team … Read More
DVCon India 2026by Admin on 08-03-2026 at 6:42 pm
The premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits.
Dear Design, Verification and Validation Community,
It is my great pleasure to welcome you to DVCon India 2026, taking place September 1-3, 2026, at Radisson… Read More
By Mauli Shah, Product Engineer, Siemens
Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More
Join Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification. As AI and machine learning are increasingly integrated into EDA workflows—from design generation to verification and system-level optimization—new challenges are emerging around… Read More
Webinar Overview:
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal “apps”.
So, what is the truth of the matter? Can non-specialist… Read More
This seminar will provide design engineers and verification teams with the knowledge and tools needed to advance their workflows using the latest AI-driven automation, intelligent verification platforms, and industry-proven methodologies.
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