Verification Futures Conference 2024 UK

Verification Futures Conference 2024 UK
by Admin on 03-07-2024 at 3:25 pm

About

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their … Read More


Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
by Admin on 03-07-2024 at 3:13 pm

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than

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Cadence – AI/ML function verification seminar

Cadence – AI/ML function verification seminar
by Admin on 02-07-2024 at 11:11 pm

As advances in AI technology, such as generative AI, are expanding demand for semiconductors, cutting-edge semiconductor design technology is also incorporating artificial intelligence (AI) and machine learning (ML) technology.

As a pioneer in providing solutions that utilize AI technology in the verification field, Read More


Webinar: Accelerating AI-driven Debug and Verification Management with Next-Gen Verdi Platform

Webinar: Accelerating AI-driven Debug and Verification Management with Next-Gen Verdi Platform
by Admin on 01-16-2024 at 4:09 pm

Join us for an exclusive Synopsys webinar highlighting the recently unveiled, cutting-edge advancements in the next-generation Synopsys Verdi platform.  Explore the power of AI-driven debug and new root cause analysis engines designed to speed-up bug finding, while experiencing enhanced usability through a refreshed

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Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
by Admin on 01-08-2024 at 2:00 pm

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly

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Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges
by Admin on 01-08-2024 at 1:39 pm

Thursday, February 8, 2024 | 9-10 a.m. PT

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power

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Making UVM faster through a new configuration system

Making UVM faster through a new configuration system
by Daniel Payne on 12-26-2023 at 10:00 am

Elapsed Time min

The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More


Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP
by Admin on 11-28-2023 at 4:42 pm

Summary

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging

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Webinar: Auto-generation of Verification Infrastructure for IP to SoC

Webinar: Auto-generation of Verification Infrastructure for IP to SoC
by Admin on 11-15-2023 at 3:44 pm

DVClub Europe Meeting –November 2023

Agenda (BST):

12.00 GMT – Welcome and Introduction

Mike Bartley,Tessolve

12.00 GMT – Saving Development Time by Automating Verification infra from specifications

Anupam Bakshi, Agnisys

12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification

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HLS Design and Verification Seminar 2023 

HLS Design and Verification Seminar 2023 
by Admin on 11-07-2023 at 4:23 pm

We will be holding a high-level synthesis technical forum. The past few years have been held online, but this year we were able to return to the venue. We have prepared a variety of proposals, including success stories and new technology updates related to high-level design and verification, so please come and join us, even if

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