Advanced nodes brings in complexity in designs leading to high Physical verification times with increasing number of DRC errors and more verification iterations. Calibre responds to the need for reduced cycle time with revolutionary

June 25, 2020July 1, 2020

Nobody ever lost their job for spending too much on hardware verification, did they?

Nobody ever lost their job for spending too much on hardware verification, did they?
by Daniel Nenni on 06-25-2020 at 6:00 am
Categories: EDA, IP
5 Comments

A paper was published last month on the Acuerdo Consultancy Services website authored by Joe Convey of Acuerdo and Bryan Dickman of Valytic Consulting. Joe and Bryan spent combined decades in the Semi and EDA World which means they have a great understanding of hardware bugs first hand, absolutely.

Here is a quick summary… Read More

May 19, 2020June 22, 2020

Is Mutation Testing Worth the Effort? Innovation in Verification

Is Mutation Testing Worth the Effort? Innovation in Verification
by Bernard Murphy on 05-19-2020 at 6:00 am
Categories: Cadence, EDA
5 Comments

Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.

The Innovation

This month’s pick is Which Software … Read More

April 2, 2020July 6, 2020

Private Datacenter Safer than the Cloud? Dangerously Wrong.

Private Datacenter Safer than the Cloud? Dangerously Wrong.
by Bernard Murphy on 04-02-2020 at 6:00 am
Categories: EDA, Security
7 Comments

The irony around this topic in the middle of the coronavirus scare – when more of us are working remotely through the cloud – is not lost on me. Nevertheless, ingrained beliefs move slowly so it’s still worth shedding further light. There is a tribal wisdom among chip designers that what we do demands much higher security than any other… Read More

December 18, 2019January 3, 2020

A VIP to Accelerate Verification for Hyperscalar Caching

A VIP to Accelerate Verification for Hyperscalar Caching
by Bernard Murphy on 12-18-2019 at 6:00 am
Categories: EDA, IP, Mentor, a Siemens Business

Non-volatile memory (NVM) is finding new roles in datacenters, not currently so much in “cold storage” as a replacement for hard disk drives, but definitely in “warm storage”. Warm storage applications target an increasing number of functions requiring access to databases with much lower latency than is possible through paths… Read More

July 16, 2019August 3, 2019

WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis
by Randy Smith on 07-16-2019 at 10:00 am
Categories: Breker Verification Systems, EDA

I’ve been following the evolution of the verification space for a very long time including several stints consulting to formal verification companies. It has always been interesting to me to see how so many diverse verification techniques emerge and been used, but without much unification of the approaches. With the emergence… Read More

April 17, 2019January 8, 2020

Hogan Fireside Chat with Paul Cunningham at ESDA

Hogan Fireside Chat with Paul Cunningham at ESDA
by Bernard Murphy on 04-17-2019 at 7:00 am
Categories: Automotive, Cadence, EDA, Security

If you’re in verification and you don’t know who Paul Cunningham is, this is a guy you need to have on your radar. Paul has risen through the Cadence ranks fast, first in synthesis and now running the verification group, responsible for about a third of Cadence revenue and a hefty percentage of verification tooling in the semiconductor… Read More

July 11, 2018January 10, 2020

Cadence’s Smarter and Faster Verification in the Era of Machine Learning, AI, and Big Data Analytics Panel

Cadence’s Smarter and Faster Verification in the Era of Machine Learning, AI, and Big Data Analytics Panel
by Camille Kokozaki on 07-11-2018 at 12:00 pm
Categories: Cadence, EDA, Events

I attended on Monday, June 25, DAC’s Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).… Read More

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