In the race to deliver ever-larger SoCs under shrinking schedules, simulation is becoming a bottleneck. With debug cycles constrained by long iteration times—even for minor code changes—teams are finding traditional flows too rigid and slow. The problem is further magnified in continuous integration and continuous deployment… Read More
Tag: verification
Verification Futures Conference 2025
Why Attend?
Attendees will gain access to cutting-edge technical content and expert presentations in:
- AI-Enhanced Semiconductor and IP Design
- Next-Generation IP Architectures and Verification Strategies
- Innovative Design Methodologies and Flows
- Emerging and Breakthrough Technologies
- Design for AI/ML Acceleration
Webinar: Tackling Emerging DFT Verification Challenges with Questa One
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off.
Come learn how the Questa One DFT Verification solution, combined
Webinar: Enhancing Automotive Safety Verification Using Questa One Sim FX
Wednesday, June 4 – 8:00 AM Pacific
In today’s automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge fault simulation platform designed specifically for complex automotive designs. We’ll
Webinar: Verifying Chiplet-based Systems
Verifying Chiplet-based Systems (online)
As the semiconductor industry increasingly embraces chiplet-based architectures, the complexity of system integration and verification has grown exponentially. Verifying these modular systems demands new approaches, tools, and collaboration across design and verification… Read More
Accellera at the 62nd Design Automation Conference – Luncheon Panel
“Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?”
Industry leaders will discuss the transformative role of AI in semiconductor design and verification. As AI rapidly evolves, its potential to reduce costs, shorten time-to-market and address impending talent shortages is becoming… Read More
Webinar: Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author
Wednesday, May 28 – 8:00 AM Pacific
Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs.
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with
Webinar: Solving the Semiconductor Verification Crisis: From Problem to Productivity
Wednesday, May 21 – 8:00 AM Pacific
The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.
This challenge is compounded by demands for Enhanced security, Reduced power
Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management
Featured Speakers:
- Gopinath Lakshmi Narasimhan, Sr. Architect Applications Engineer
- Robert Ruiz, Sr. Director, Product Management
Why You Should Attend:
- Discover the innovative capabilities of Synopsys VC Execution Manager for streamlined verification processes.
- Learn about the seamless integration of advanced AI/ML
Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles
Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,