Tag: verification

Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management

Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management
by Admin on 04-18-2025 at 9:48 am

Featured Speakers:

  • Gopinath Lakshmi Narasimhan, Sr. Architect Applications Engineer
  • Robert Ruiz, Sr. Director, Product Management

Why You Should Attend:

  • Discover the innovative capabilities of Synopsys VC Execution Manager for streamlined verification processes.
  • Learn about the seamless integration of advanced AI/ML
… Read More

Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles

Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles
by Admin on 03-28-2025 at 12:31 pm

Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,

… Read More

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 03-27-2025 at 1:04 pm

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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AlphaDesign AI Experts Wade into Design and Verification

AlphaDesign AI Experts Wade into Design and Verification
by Bernard Murphy on 03-06-2025 at 6:00 am
Categories: AI, Alpha Design AI, EDA

DVCon 2025 talk min

I mentioned in an earlier blog that multiple presentations at DVCon 2025 went all-in on AI-assisted design and verification. The presentation was one such example, looking very much at top-down AI-expert application of agentic flows to design and verification. AlphaDesign is a new startup out of UC Santa Barbara headed by William… Read More

Webinar: Automotive Safety Implementation with Cadence Solutions

Webinar: Automotive Safety Implementation with Cadence Solutions
by Admin on 01-24-2025 at 1:24 pm

Don’t miss our upcoming webinar, where we’ll explore the importance of safety in automotive design. This session will focus on the customer’s high demand for integrated safety flows in verification, digital, and analog design. We’ll showcase the exceptional value of the Midas Safety Platform for… Read More

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Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics

Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics
by Kalar Rajendiran on 09-26-2024 at 10:00 am
Categories: Analytics, EDA, Siemens EDA

RDC Verification using Data Analysis Techniques

The complexity of System-on-Chip (SoC) designs continues to rise at an accelerated rate, with design complexity doubling approximately every two years. This increasing complexity makes verification a more difficult and time-consuming task for design engineers. Among the key verification challenges is managing reset domain… Read More

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3DIC Verification Methodologies for Advanced Semiconductor ICs

3DIC Verification Methodologies for Advanced Semiconductor ICs
by Kalar Rajendiran on 06-06-2024 at 10:00 am
Categories: 3D IC, Analytics, Chiplet, EDA, Siemens EDA

3DIC Flow Challenges

At the recent User2user conference, Amit Kumar, Principal Hardware Engineer, Microsoft, shared the company’s experience from building a 3DIC SoC and highlighted Siemens EDA tools that were used. The following is a synthesis of core aspects of that talk.

3DIC Challenges

Despite the numerous advantages of 3DIC technology, its… Read More

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Making UVM faster through a new configuration system

Making UVM faster through a new configuration system
by Daniel Payne on 12-26-2023 at 10:00 am
Categories: EDA, Siemens EDA

Elapsed Time min

The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More

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A New Verification Conference Coming to Austin

A New Verification Conference Coming to Austin
by Bernard Murphy on 08-15-2023 at 6:00 am
Categories: Events, Semiconductor Services

Actually not so new, just new to us in the US. Verification Futures is already well established as a Tessolve event with a 10-year track record in the UK. This year they are bringing the conference to Austin on September 14th (REGISTER HERE).

While DVCon is an ever-popular event for sharing verification ideas, it isn’t always accessible… Read More