Verification Completion: When is enough enough?  Part I

Verification Completion: When is enough enough?  Part I
by Dusica Glisic on 09-30-2021 at 6:00 am

Tunnel min

Verification is a complex task that takes the majority of time and effort in chip design. Veriest shares customer views on what this means. We are an ASIC services company, and we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.

In this “Verification Talks”… Read More


Challenges of AV Simulation and Verification

Challenges of AV Simulation and Verification
by Admin on 07-22-2021 at 12:00 am

LIVE WEBINAR | 22 JULY 2021 | 01:00 PM EST

Simcenter has many unique solutions for ADAS system development. Learn more in this webinar series – Addressing the engineering challenges of electrification.

This session will shift focus to reflect upon the unique challenges of bringing an autonomous vehicle to market and

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Boost Verification Productivity with PSS 2.0 and Perspec

Boost Verification Productivity with PSS 2.0 and Perspec
by Admin on 06-10-2021 at 12:00 am

June 10, 2021

Overview

SoC level verification and validation is often the bottleneck of chip design projects due to lack of methodology and automation for creating system level stimulus and limited content reuse. Complex system use-cases, involve interactions between different elements in the system, are hard to write, model

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Accellera Unveils PSS 2.0 – Production Ready

Accellera Unveils PSS 2.0 – Production Ready
by Bernard Murphy on 05-27-2021 at 6:00 am

PSSToolFlow min

I recently had a discussion with Tom Fitzpatrick of Siemens and Faris Khundakjie of Intel on the latest release of the Portable Test and Stimulus Standard (PSS). Faris chairs the PSS working group and Tom is vice-chair. In what follows I synthesize feedback from both, sometimes I call out interesting individual comments. My first… Read More


What’s the Recipe for Efficient Analog IC Design and Verification?

What’s the Recipe for Efficient Analog IC Design and Verification?
by Admin on 05-19-2021 at 12:00 am

Overview

For analog IC designers, the most important capability is rapid simulation of an accurate model of their circuits. Early in the design process, they explore architectures and novel approaches and need an agile simulation flow that gives them confidence that the implemented design is capable of meeting the system specs.

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Why is CDC Verification for FPGA Designs important

Why is CDC Verification for FPGA Designs important
by Admin on 05-11-2021 at 12:00 am

FPGA Designs have become very complex today, most FPGA Designs could be considered System On Chip Designs because they contain multiple complex system components with different protocol interfaces like AMBA, PCIe, Ethernet, USB, just to name a few of the most popular ones. The complexity itself is already a challenge for verification

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Automatic End-to-End Formal Verification of RISC-V Processors

Automatic End-to-End Formal Verification of RISC-V Processors
by Admin on 03-11-2021 at 12:00 am

Overview

Processor verification has always been a significant challenge. With the open-source RISC-V® ISA, we see an emerging revolution for processor design with lots of new commercial-grade processors for a wide range of applications ranging from embedded, storage, automotive, AI/ML, 5G, to IoT. While power, performance,

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Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.

Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.
by Raul Perez on 02-09-2021 at 10:00 am

iStock 1176843522

This article about verification is part 2 of a two article series. Please see part 1 on validation HERE.

Verification is a field that has emerged as its own discipline. It’s no longer being relegated to an activity led by the design team to which time is allocated as long as it doesn’t get in the way of designing. Chip companiesRead More


CDC, Low Power Verification. Mentor and Cypress Perspective

CDC, Low Power Verification. Mentor and Cypress Perspective
by Bernard Murphy on 01-13-2021 at 6:00 am

CDC Low Power

Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More