Verification is a complex task that takes the majority of time and effort in chip design. Veriest shares customer views on what this means. We are an ASIC services company, and we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.
In this “Verification Talks”… Read More
LIVE WEBINAR | 22 JULY 2021 | 01:00 PM EST
This session will shift focus to reflect upon the unique challenges of bringing an autonomous vehicle to market and
June 10, 2021
Overview
SoC level verification and validation is often the bottleneck of chip design projects due to lack of methodology and automation for creating system level stimulus and limited content reuse. Complex system use-cases, involve interactions between different elements in the system, are hard to write, model
I recently had a discussion with Tom Fitzpatrick of Siemens and Faris Khundakjie of Intel on the latest release of the Portable Test and Stimulus Standard (PSS). Faris chairs the PSS working group and Tom is vice-chair. In what follows I synthesize feedback from both, sometimes I call out interesting individual comments. My first… Read More
Overview
For analog IC designers, the most important capability is rapid simulation of an accurate model of their circuits. Early in the design process, they explore architectures and novel approaches and need an agile simulation flow that gives them confidence that the implemented design is capable of meeting the system specs.
FPGA Designs have become very complex today, most FPGA Designs could be considered System On Chip Designs because they contain multiple complex system components with different protocol interfaces like AMBA, PCIe, Ethernet, USB, just to name a few of the most popular ones. The complexity itself is already a challenge for verification
Overview
Processor verification has always been a significant challenge. With the open-source RISC-V® ISA, we see an emerging revolution for processor design with lots of new commercial-grade processors for a wide range of applications ranging from embedded, storage, automotive, AI/ML, 5G, to IoT. While power, performance,
This article about verification is part 2 of a two article series. Please see part 1 on validation HERE.
Verification is a field that has emerged as its own discipline. It’s no longer being relegated to an activity led by the design team to which time is allocated as long as it doesn’t get in the way of designing. Chip companies… Read More
Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More
RISC-V has been trending ever since it landed on SemiWiki in 2016. Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.
Two things… Read More
