Tag: verification
CadenceCONNECT: Tech Days Europe 2024 – Eindhoven
CadenceCONNECT: Tech Days Europe 2024 – Leuven
CadenceCONNECT: Tech Days Europe 2024 – Sophia Antipolis
CadenceCONNECT: Tech Days Europe 2024 – Milan
CadenceCONNECT: Tech Days Europe 2024 – Munich
Date: Thursday, May 16, 2024
Venue: Holiday Inn Munich – City Centre
Location: Hochstrasse 3, Munich, 81669 Germany
Parking: On-site parking for €20 per day.
You will receive further information in your registration confirmation email.
Formal Verification – DVClub Europe Meeting
Formal Verification
Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting
Verification Futures Conference 2024 UK
About
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their … Read More
Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than
Cadence – AI/ML function verification seminar
As advances in AI technology, such as generative AI, are expanding demand for semiconductors, cutting-edge semiconductor design technology is also incorporating artificial intelligence (AI) and machine learning (ML) technology.
As a pioneer in providing solutions that utilize AI technology in the verification field, … Read More