Synopsys VC Formal DPV Virtual Workshop Series Day 2

Synopsys VC Formal DPV Virtual Workshop Series Day 2
by Admin on 01-18-2023 at 3:10 pm

Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry’s best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath… Read More


CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation
by Admin on 01-16-2023 at 2:09 pm

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More


DVClub Europe Meeting: RISC-V Verification Strategies

DVClub Europe Meeting: RISC-V Verification Strategies
by Admin on 11-21-2022 at 1:20 pm

Tuesday 29th November, 2022

12:00 – 13:30 GMT

RISC-V Verification Strategies

With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC.

About DVClub

The principal

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Truechip Introduces Automation Products – NoC Verification and NoC Performance

Truechip Introduces Automation Products – NoC Verification and NoC Performance
by Kalar Rajendiran on 11-07-2022 at 10:00 am

Truechip NoC Automation Product

While Truechip has established itself as a global provider of verification IP (VIP) solutions, they are always on the lookout for strategic IP needs from their customer base. Over the last several years, a solid market for Network-on-Chip (NoC) IP has grown, driven by the need to rapidly move data across a chip. Concurrently, the… Read More


Webinar: Code Review for System Architects

Webinar: Code Review for System Architects
by Admin on 11-02-2022 at 11:59 am

* Company email is required*

Register management tools have been used mostly in a bottom-up approach. There are some documents and/or spreadsheets created by the System Architects that are delivered to the design and verification teams. They then start capturing the HW/SW interface of the peripheral IPs in their in-house or

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New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development

New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development
by Kalar Rajendiran on 10-24-2022 at 10:00 am

1 Cadence Joint Enterprise Data and AI JedAI Platform

Without data, there is no computing field to talk about, no technology world to awe at and not much of a semiconductor industry to work in. There is no argument that data is the foundational piece for everything, has been to date and will continue to be. While processing an application’s input data is essential to serve the intended… Read More


Cadence TECHTALK: Low-Power Verification using Xcelium Simulation

Cadence TECHTALK: Low-Power Verification using Xcelium Simulation
by Admin on 10-19-2022 at 2:12 pm

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. In this webinar, the focus will be on the functional verification of the RTL with the power intent

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Webinar: Improving Efficiency and Quality of Verification Environments with Automation

Webinar: Improving Efficiency and Quality of Verification Environments with Automation
by Admin on 09-27-2022 at 9:55 pm

Synopsys Webinar: Tuesday, October 18, 2021 | 10 a.m. Pacific

REGISTER HERE

Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification

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Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Admin on 09-14-2022 at 1:57 pm

Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit

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