Webinar: Accelerating AI-driven Debug and Verification Management with Next-Gen Verdi Platform

Webinar: Accelerating AI-driven Debug and Verification Management with Next-Gen Verdi Platform
by Admin on 01-16-2024 at 4:09 pm

Join us for an exclusive Synopsys webinar highlighting the recently unveiled, cutting-edge advancements in the next-generation Synopsys Verdi platform. Explore the power of AI-driven debug and new root cause analysis engines designed to speed-up bug finding, while experiencing enhanced usability through a refreshed

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
by Admin on 01-08-2024 at 2:00 pm

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges
by Admin on 01-08-2024 at 1:39 pm

Thursday, February 8, 2024 | 9-10 a.m. PT

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power

December 26, 2023March 7, 2024

Making UVM faster through a new configuration system

The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP

Webinar: Multi-Die System Verification with Siemens Avery UCIe VIP
by Admin on 11-28-2023 at 4:42 pm

Summary

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging

Webinar: Auto-generation of Verification Infrastructure for IP to SoC

Webinar: Auto-generation of Verification Infrastructure for IP to SoC
by Admin on 11-15-2023 at 3:44 pm

DVClub Europe Meeting –November 2023

Agenda (BST):

12.00 GMT – Welcome and Introduction

Mike Bartley,Tessolve

12.00 GMT – Saving Development Time by Automating Verification infra from specifications

Anupam Bakshi, Agnisys

12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification

HLS Design and Verification Seminar 2023　

HLS Design and Verification Seminar 2023　
by Admin on 11-07-2023 at 4:23 pm

Webinar: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US)

Webinar: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US)
by Admin on 10-25-2023 at 4:01 pm

LIVE WEBINAR: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US)

Philipp Wagner, cocotb and Hardware/Software Engineer at lowRISC

Thursday, November 9, 2023

11:00 AM – 12:00 PM (PST)

Abstract:

cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such… Read More

RISC-V in Space

RISC-V in Space
by Admin on 10-25-2023 at 3:50 pm

About this event

7 hours
Mobile eTicket

Tenstorrent is hosting a meet up in Denver aimed at practitioners and entrepreneurs developing electronic systems and components for space applications. Alongside partners Codasip, Cycuity, Breker Systems, Imperas, RISC AI, Synopsys, and Arteris IP we are excited to invite you to explore

Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow

Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow
by Admin on 10-04-2023 at 5:11 am