The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More
DVCon Japan 2024
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits. This conference will have highly technical content, focusing on the practical aspects … Read More
