Truechip Introduces Automation Products – NoC Verification and NoC Performance

While Truechip has established itself as a global provider of verification IP (VIP) solutions, they are always on the lookout for strategic IP needs from their customer base. Over the last several years, a solid market for Network-on-Chip (NoC) IP has grown, driven by the need to rapidly move data across a chip. Concurrently, the TileLink interface specification has also been gaining broad adoption in SoCs for implementing cache-coherent transactions. This created a need for a NoC IP to work with the TileLink protocol. Truechip seized this opportunity last year and introduced their NoC Silicon IP that leverages the TileLink interface specification. An earlier SemiWiki post discussed Truechip’s NoC Silicon IP. While the TileLink specification was originally developed to work with the RISC-V architecture, it actually supports other instruction set architectures (ISAs) too.

Truechip’s NoC Silicon IP provides chip architects and designers with an efficient way to connect multiple TileLink based master and slave devices for reduced latency, power, and area. It also helps reduce physical interconnect routing and use of resources inside an SoC. Yet another constant demand in the chip world is the need for faster and more efficient verification of designs and IP. The ever increasing design complexities directly expand the scope of verification challenges for achieving full coverage. New verification methodologies are needed to increase the efficiency and efficacy of testing highly complex designs. Any level of automation that can be brought into the life of a verification engineer will help ease the burden, leading to faster creation of testbenches. Truechip has seized this opportunity to introduce some automation products to their customer base. Earlier this year, the company announced their Automation Products addressing NoC Verification and NoC Performance for revolutionizing the verification process.

NoC Automation Products

The different IP blocks not only need to work as per their internal specifications, they also need to interact at the system level. Verification requires checking how the various blocks interact against the specifications at the system level. Performing this task may involve manual calculations for checking against various latency requirements. Many times, this may also call for manually viewing signal waveforms. Truechip’s automation products help ease the task of verification engineers by mitigating these manual tasks, thereby reducing the time and effort needed for optimization. IP teams can more efficiently optimize their IP for maximizing bus and bandwidth utilization. Chip verification engineers and chip architects alike benefit from this automation.

NoC Performance Product

Truechip’s NoC Performance is a robust performance analyzer for NoC IP/SoC and supports fully compliant standard Bus interface ports like AXI, AHB, APB, and TileLink. It comes with compliance and regression test suites along with exhaustive set of assertions and coverage points. The product offers consistency of interface, installation, operation and documentation across all of Truechip’s VIP solutions.

Some Salient Features

• • Per interface latency and NoC latency
  • Latency variation over transactions
  • Transaction Tracing
  • Per interface bandwidth
  • Master and Slave Interface comparisons (in terms of bandwidth and Latency)
  • Consolidated summary timeline for different performance numbers in single window
  • Statistics for different types of commands encountered on bus Bandwidth (GBps) and throughput
  • Actual Data transfer
  • Time window to select the duration for computing utilization

For the complete list of features, refer to the NoC Performance Product page.

Deliverables

NoC Monitor, Scoreboard

Master and Slave Port VIP (AXI/AHB/APB/TileLink)

TruEYE™ GUI for transaction level information

Test Suite:

Basic and Directed Protocol Tests

Random Tests

Error Scenario Tests

Assertions & Coverage Point Tests

Integration Guide, User Manual, FAQ, and Release Notes

NoC Verification IP

Truechip’s NoC Verification IP provides an efficient way to verify the components interfacing with any type of NoC IP or SoC. It is a light weight VIP with an easy, plug-and-play interface that minimizes the hit on design cycle times. The solution comes with a GUI based testbench generator (TBG) and supports fully compliant standard Bus interface ports such as AXI, AHB, APB and TileLink.  The VIP is available in native System Verilog UVM and Verilog.

Some Salient Features

• Automated Testbench creation & Integration of DUT and VIP
• Automated Test case generation for sanity tests / full verification
• End to end data score boarding
• NoC Monitor
• Regression running and analysis
• Multiple protocols and (theoretically) any number of nodes

For complete list of features, refer to the NoC Verification Product page.

Deliverables

TruEYE-TBG (Testbench generator)

Master and Slave Port VIP (AXI/AHB/APB/TileLink)

Test Suite:

Basic and Directed Protocol Tests

Random Tests

Error Scenario Tests

Assertions & Cover Point Tests

Integration Guide, User Manual, FAQ, and Release Notes

About Truechip

Truechip, the Verification IP specialist, is a leading provider of Design and Verification solutions. It has been serving customers for more than a decade. Its solutions help accelerate the design cycle, lowers the cost of development and reduces the risks associated with the development of ASICs, FPGAs, and SoCs. The company has a global footprint with sales coverage across North America, Europe and Asia. Truechip provides the industry’s first 24×7 support model with specialization in VIP integration, customization and SoC Verification.

For more information, refer to Truechip website.

Also Read:

Truechip: Customer Shipment of CXL3 VIP and CXL Switch Model

Truechip’s Network-on-Chip (NoC) Silicon IP

Truechip’s DisplayPort 2.0 Verification IP (VIP) Solution