Tag: noc

Webinar: Connecting Chiplets Isn’t Enough – Solving the Data Movement Challenge in Multi-Die Systems

Webinar: Connecting Chiplets Isn’t Enough – Solving the Data Movement Challenge in Multi-Die Systems
by Admin on 10-27-2026 at 11:23 pm

Thursday, November 5, 2026

11:00am PST | 2:00pm EST | 20:00 CET

As SoCs evolve into multi-die systems, getting data across a die-to-die interface is only part of the challenge. Architects must also preserve traffic behavior, bandwidth efficiency and quality of service as communication moves across physical chip boundaries.

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Connecting the Dots: Why RISC-V System Design Is Entering a New Era

Connecting the Dots: Why RISC-V System Design Is Entering a New Era
by Kalar Rajendiran on 05-04-2026 at 10:00 am
Categories: AI, Arteris, IP

Andes x Arteris Pre Verified and Silicon Proven SoC Integration

At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More

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NoC Matters: Designing the Backbone of Next-Gen AI SoCs

NoC Matters: Designing the Backbone of Next-Gen AI SoCs
by Daniel Nenni on 04-13-2026 at 10:00 am
Categories: Aion Silicon, Semiconductor Services

Arteris NoC Hardware

Modern SoC design for artificial intelligence workloads has fundamentally shifted the role of the network-on-chip (NoC) from a simple connectivity fabric to a primary architectural determinant of system performance, power, and scalability. As compute density increases and heterogeneous accelerators proliferate, data… Read More

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NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures

NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures
by Daniel Nenni on 04-09-2026 at 8:00 am
Categories: Arteris, IP

NXP announcement v4b 021026 FINAL

As edge AI systems become more centralized and compute-dense, on-chip data movement is increasingly the architectural bottleneck. NXP’s expanded deployment of Arteris network-on-chip (NoC) and cache-coherent interconnect IP highlights a broader industry trend: interconnect architecture is now a first-order design … Read More

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Axiomise Introduces nocProve to Transform NoC Design Verification

Axiomise Introduces nocProve to Transform NoC Design Verification
by Daniel Nenni on 03-12-2026 at 6:00 am
Categories: Axiomise, Semiconductor Services

Axiomise Launches nocProve for NoC Verification

Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.

The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses… Read More

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The Next Hurdle AI Systems Must Clear

The Next Hurdle AI Systems Must Clear
by Bernard Murphy on 03-11-2026 at 6:00 am
Categories: AI, Arteris, Automotive, IP

datacenter surrounded by power plants

AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of … Read More

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Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am
Categories: EDA, Synopsys

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More

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The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon

The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon
by Daniel Nenni on 12-24-2025 at 6:00 am
Categories: Aion Silicon, Semiconductor Services

10 Practical SoC Steps AION Silicon

In the fast-evolving world of semiconductor design, creating a complex System-on-Chip (SoC) requires meticulous planning to ensure performance, power efficiency, and cost-effectiveness. Aion Silicon’s white paper, authored by Piyush Singh, outlines a streamlined methodology that leverages advanced modeling… Read More

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WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs

WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs
by Admin on 12-15-2025 at 8:00 am
Categories: AI, Arteris, Events, IP

AION Silicon Arteris Webinar

By Andy Nightingale, VP of Product Management and Marketing

As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More

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Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon
by Daniel Nenni on 11-27-2025 at 8:00 am
Categories: Aion Silicon, Arteris, Events, Semiconductor Services
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square 3 (1)

The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More