Free webinar – Accelerating data processing with FPGA fabrics and NoCs

Free webinar – Accelerating data processing with FPGA fabrics and NoCs
by Tom Simon on 10-14-2019 at 10:00 am

FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More


How Should I Cache Thee? Let Me Count the Ways

How Should I Cache Thee? Let Me Count the Ways
by Bernard Murphy on 09-25-2019 at 5:00 am

Caching intent largely hasn’t changed since we started using the concept – to reduce average latency in memory accesses and to reduce average power consumption in off-chip reads and writes. The architecture started out simple enough, a small memory close to a processor, holding most-recently accessed instructions and data … Read More


An evolution in FPGAs

An evolution in FPGAs
by Tom Simon on 05-24-2019 at 5:00 am

Why does it seem like current FPGA devices work very much like the original telephone systems with exchanges where workers connected calls using cords and plugs? Achronix thinks it is now time to jettison Switch Blocks and adopt a new approach. Their motivation is to improve the suitability of FPGAs to machine learning applications,… Read More


ML and Memories: A Complex Relationship

ML and Memories: A Complex Relationship
by Bernard Murphy on 04-18-2019 at 7:00 am

No, I’m not going to talk about in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various… Read More


Qualcomm Intel Facebook and Semiconductor IP

Qualcomm Intel Facebook and Semiconductor IP
by Daniel Nenni on 03-20-2019 at 12:00 am

Image RemovedWhat does Qualcomm, Intel, and Facebook have in common? Well, for one thing they all bought network onchip communications (NoC) IP companies. As I have mentioned before, semiconductor IP is the foundation of the fabless semiconductor ecosystem and I believe this trend of acquisitions will continue. So, if you are… Read More


Why High-End ML Hardware Goes Custom

Why High-End ML Hardware Goes Custom
by Bernard Murphy on 01-30-2019 at 7:00 am

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so … Read More


Disturbances in the AI Force

Disturbances in the AI Force
by Bernard Murphy on 01-03-2019 at 7:00 am

In the normal evolution of specialized hardware IP functions, initial implementations start in academic research or R&D in big semiconductor companies, motivating new ventures specializing in functions of that type, who then either build critical mass to make it as a chip or IP supplier (such as Mobileye – intially)… Read More


On-Chip Networks at the Bleeding Edge of ML

On-Chip Networks at the Bleeding Edge of ML
by Bernard Murphy on 11-29-2018 at 7:00 am

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse… Read More


Supporting ASIL-D Through Your Network on Chip

Supporting ASIL-D Through Your Network on Chip
by Bernard Murphy on 09-20-2018 at 7:00 am

The ISO 26262 standard defines four Automotive Safety Integrity Levels (ASILs), from A to D, technically measures of risk rather than safety mechanisms, of which ASIL-D is the highest. ASIL-D represents a failure potentially causing severe or fatal injury in a reasonably common situation over which the driver has little control.… Read More


Netspeed and NSITEXE talk about automotive design trends at 55DAC

Netspeed and NSITEXE talk about automotive design trends at 55DAC
by Tom Simon on 08-02-2018 at 12:00 pm

DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More