NoC Matters: Designing the Backbone of Next-Gen AI SoCs

NoC Matters: Designing the Backbone of Next-Gen AI SoCs
by Daniel Nenni on 04-13-2026 at 10:00 am

Arteris NoC Hardware

Modern SoC design for artificial intelligence workloads has fundamentally shifted the role of the network-on-chip (NoC) from a simple connectivity fabric to a primary architectural determinant of system performance, power, and scalability. As compute density increases and heterogeneous accelerators proliferate, data… Read More


NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures

NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures
by Daniel Nenni on 04-09-2026 at 8:00 am

NXP announcement v4b 021026 FINAL

As edge AI systems become more centralized and compute-dense, on-chip data movement is increasingly the architectural bottleneck. NXP’s expanded deployment of Arteris network-on-chip (NoC) and cache-coherent interconnect IP highlights a broader industry trend: interconnect architecture is now a first-order design … Read More


Axiomise Introduces nocProve to Transform NoC Design Verification

Axiomise Introduces nocProve to Transform NoC Design Verification
by Daniel Nenni on 03-12-2026 at 6:00 am

Axiomise Launches nocProve for NoC Verification

Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.

The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses… Read More


The Next Hurdle AI Systems Must Clear

The Next Hurdle AI Systems Must Clear
by Bernard Murphy on 03-11-2026 at 6:00 am

datacenter surrounded by power plants

AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More


The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon

The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon
by Daniel Nenni on 12-24-2025 at 6:00 am

10 Practical SoC Steps AION Silicon

In the fast-evolving world of semiconductor design, creating a complex System-on-Chip (SoC) requires meticulous planning to ensure performance, power efficiency, and cost-effectiveness. Aion Silicon’s white paper, authored by Piyush Singh, outlines a streamlined methodology that leverages advanced modeling… Read More


WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs

WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs
by Admin on 12-15-2025 at 8:00 am

AION Silicon Arteris Webinar

By Andy Nightingale, VP of Product Management and Marketing

As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More


Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon
by Daniel Nenni on 11-27-2025 at 8:00 am

square 3 (1)

The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More


Boosting SoC Design Productivity with IP-XACT

Boosting SoC Design Productivity with IP-XACT
by Daniel Payne on 11-17-2025 at 10:00 am

IP XACT min

IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.

What is IP-XACT?

IP-XACT… Read More


The IO Hub: An Emerging Pattern for System Connectivity in Chiplet-Based Designs

The IO Hub: An Emerging Pattern for System Connectivity in Chiplet-Based Designs
by Bernard Murphy on 09-17-2025 at 6:00 am

Disaggregation of NoCs min

In chiplet-based design we continue the march of Moore’s Law by scaling what we can put in a semiconductor package beyond the boundaries of what we can build on a single die. This style is already gaining traction in AI applications, high performance computing, and automotive, each of which aims to scale out to highly integrated … Read More