Cadence® Janus™ Network-on-Chip (NoC)

A Network-on-Chip (NoC) IP addresses the challenges of interconnect complexity in SoCs by significantly reducing wiring congestion and providing a scalable architecture. It allows for efficient communication among numerous initiators and targets with minimal latency and high speed. A NoC facilitates design changes, enabling quick iterations to meet specific design goals regarding bandwidth, latency, area, and power. Cadence recently expanded their system IP portfolio with the addition of the Janus NoC IP. At the surface, it may prompt the question, what is the big deal, NoC IP is not a new concept and this type of IP is common in the industry. I got deeper insights by chatting with Cadence’s George Wall, group director of product marketing and Ronen Perets, senior product marketing manager, both in the Cadence Silicon Solutions Group.

Integral Subsystem Component

The Cadence Janus NoC IP is in response to requests from the company’s customer base for expanded system-level solutions. This IP is an integral part of Cadence’s silicon solutions strategy, aimed at providing significant value to its licensee partners. It leverages Cadence’s extensive design expertise and best-in-class verification tools and methodologies, ensuring that the NoC meets the highest standards of quality and performance. This strategic addition enhances Cadence’s portfolio, making it a crucial component for advanced SoC designs. The IP is designed to handle inter-chiplet communication efficiently, using programmable routing and supporting dynamic configurations. The NoC is designed to support the evolving multi-chip module and chiplet-based design architectures. This adaptability ensures future-proofing for increasingly complex SoC designs.

Leverages Cadence’s Extensive Portfolio of Software and Hardware Offerings

Cadence offers a comprehensive system solution that includes processors with a full set of Software Development Tools (SDT) and Software Development Kits (SDK), Digital Signal Processors (DSP), libraries, and frameworks, I/O controllers to facilitate various interface requirements, and PHY for physical layer implementations ensuring reliable data transmission. The Cadence Janus NoC enhances performance, power, and area (PPA) by efficiently managing high-speed communications within and between silicon components with minimal latency. By optimizing RTL for PPA and utilizing packetized messages, the NoC reduces wire count and mitigates timing closure challenges, thereby accelerating time to market.

Architectural Exploration and Verification

Cadence offers extensive simulation and emulation options to support architectural exploration and verification. The Palladium Accelerator provides full visibility and increases simulation speed, making it ideal for extensive performance benchmarking. The Protium Platform maps the full SoC onto FPGAs for extremely fast emulation, which is particularly useful for debugging at the SoC level. SystemC modeling allows for fast debugging and firmware bring-up using a functional SystemC model generated alongside the RTL. Additionally, the Cadence Helium Virtual and Hybrid Studio enables the mixing of different model types and running each module on different platforms, facilitating performance monitoring and rapid iteration.

Designed for Ease of Use

The Cadence Janus NoC is designed with ease of use in mind, offering a highly configurable and flexible architecture. It features a GUI configuration tool that allows users to easily configure and generate NoC RTL, and comes with a comprehensive package that includes synthesis scripts, a testbench, and a functional model, streamlining the design process. Early optimization of NoC design is facilitated through iterative design exploration and performance validation using Cadence simulation and emulation technologies, along with the Cadence System Performance Analysis (SPA) tool, ensuring that the architecture meets performance needs.

Cadence Janus NoC Architecture

The Cadence Janus NoC architecture consists of three main components: the Initiator Endpoint Adapter (IEA), which connects initiator endpoints to the NoC; the Target Endpoint Adapter (TEA), which connects target endpoints to the NoC; and the Routing Node, which routes packets between IEAs and TEAs to their respective destinations. A typical NoC comprises multiple IEAs, TEAs, and routing nodes. These nodes are interconnected, allowing messages to traverse from origin to destination efficiently. Routing nodes can be configured to optimize bandwidth and latency, with pipeline stages added to maintain the desired speed despite physical distance challenges.

Summary

The Cadence Janus NoC architecture offers a scalable, efficient, and adaptable approach to addressing the complex interconnect requirements of modern SoCs. With advanced configuration tools, robust simulation and emulation options, and comprehensive power management and verification strategies, Cadence’s NoC technology empowers designers to create optimized, high-performance SoCs efficiently and effectively. By managing high-speed communications efficiently, the Janus NoC helps design teams achieve their PPA targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. As the industry continues to evolve, Cadence Janus NoC stands as a future-proof platform, enabling designers to meet current and future demands with confidence.

You can learn more about the Janus NoC System IP from here.

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