Date/Time:
October 23, 2020
10:00am – 2:00pm PDT
Overview
Cadence Is Joining the Virtual Clastech 2020!
Clastech is a technical symposium held yearly highlighting recent developments in RF and microwave technologies as a joint effort by the local chapters of the IEEE Microwave Theory and Techniques Society (MTT-S)
Hands down, without a doubt, the most interesting CEO in semiconductors is Lip-Bu Tan, founder of Walden Capitol and current CEO of Cadence Design Systems. If you want to talk about a man with a plan it’s Lip-Bu Tan.
Before we get into the fireside chat between Tom Caufield and Lip-Bu at the GTC 2020 Virtual event let’s do a quick biography:… Read More
A Digital Event – October 21 – 22
Ready to share and discuss the latest design and verification best practices with your peers from around the world?
It’s time for our annual Jasper® User Group Conference. This in-depth technical conference connects designers, verification engineers, and engineering managers
A Digital Experience – October 21
Overview
CadenceCONNECT will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues
Overview
Static low-power verification enables engineers to verify and debug multimillion-gate designs optimized for low power, without complex and time-consuming simulations. However, understanding these IEEE 1801 violations and diagnosing the root cause can become challenging without a user-friendly debug infrastructure.
Overview
Biggest loss in designer productivity occurs in the editing and tweaking of designs leading to lowest performance gain per unit of time. Under a very tight schedule, it comes down to zero. It can be significantly improved with Cadence’s Allegro PCB Productivity Toolbox.
Cadence’s Allegro PCB Productivity Toolbox
In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More
A Digital Experience
August 11-13, 2020
CadenceLIVE 2020 is Going Digital!
For the last fifteen years, CadenceLIVE Silicon Valley has brought together technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity.
As our top priority continues to be the health
August 4-6, 2020
Meet with Cadence at the IMS online event and learn how to better address your RF/microwave and multi-fabric design challenges, including electromagnetic (EM) analysis, verification, and cross-fabric implementation. With the addition of AWR’s technologies and talent, we have expanded Cadence’s reach
Accelerate Design Productivity with Virtuoso ADE Explorer and Assembler
Date: Wednesday, July 08, 2020
Time: 10:00 BST / 11:00 CEST / 14:30 IST / 17:00 CST
Questions about this event?
Send email to: eur_training@cadence.com
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Intel TSMC Update!