Methodology for Aging-Aware Static Timing Analysis

Methodology for Aging-Aware Static Timing Analysis
by Tom Dillinger on 12-28-2021 at 10:00 am

char STA flow

At the recent Design Automation Conference, Cadence presented their methodology for incorporating performance degradation measures due to device aging into a static timing analysis flow. [1] (The work was a collaborative project with Samsung Electronics.)  This article reviews the highlights of their presentation.

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More Than Moore and Charting the Path Beyond 3nm

More Than Moore and Charting the Path Beyond 3nm
by Kalar Rajendiran on 12-22-2021 at 10:00 am

Cadence AIML Technologies

The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More


CadenceTECHTALK: Using Protium Black-Box Flow to Implement Native Interfaces

CadenceTECHTALK: Using Protium Black-Box Flow to Implement Native Interfaces
by Admin on 12-16-2021 at 12:00 am

Using Protium Black-Box Flow to Implement Native Interfaces

December 16, 2021

Overview

Protium prototyping platform provides by far the fastest and easiest bring-up (time to prototype) of any prototype system in the market, combined with vastly higher runtime performance than emaulation system. But what if…

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CadenceCONNECT: Fostering a Photonics Ecosystem for Sustainable Adoption

CadenceCONNECT: Fostering a Photonics Ecosystem for Sustainable Adoption
by Admin on 12-07-2021 at 12:00 am

Fostering a Photonics Ecosystem for Sustainable Adoption

December 7 – 9

Overview / Summary

For the past two decades, integrated photonics has made tremendous progress and is now offered by industry-leading semiconductor companies. However, outside of its most common use in data communications, adoption is still

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CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP

CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
by Admin on 11-17-2021 at 12:00 am

Power and Energy Optimization Using Tensilica IP

November 17, 2021

Overview

Design teams are facing the challenges of having to add more and more processing and programmable capabilities in their SoC in order to adapt and implement the latest and greatest algorithms during the lifecycle of their products, but at the same time

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Battery Sipping HiFi DSP Offers Always-On Sensor Fusion

Battery Sipping HiFi DSP Offers Always-On Sensor Fusion
by Tom Simon on 11-11-2021 at 10:00 am

HiFi DSP

Earbuds are one of the fastest growing market segments, which is creating the need for audio DSPs with higher performance and a smaller energy footprint. More than just being wireless speakers – earbuds, and wearables for that matter, have become a sophisticated extension of the user interface of phones and laptops, etc.… Read More


CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs

CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs
by Admin on 11-10-2021 at 12:00 am

Taming the Challenges of Advanced Node Digital Designs

November 10, 2021

Overview

Although new challenges arise with each node, the move from bulk technologies to advanced node technologies marks a distinctive shift in complexity. Some of the important factors to consider are new devices, challenging and competing design

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CadenceTECHTALK: Boost LPDDR5 Verification from IP to System Level

CadenceTECHTALK: Boost LPDDR5 Verification from IP to System Level
by Admin on 11-09-2021 at 12:00 am

Boost LPDDR5 Verification from IP to System-Level

November 9

Overview

Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies

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CadenceTECHTALK: Intelligent Cross-Platform Workflows for RF PCB Integration

CadenceTECHTALK: Intelligent Cross-Platform Workflows for RF PCB Integration
by Admin on 11-02-2021 at 12:00 am

Intelligent Cross-Platform Workflows for RF PCB Integration

November 2, 2021

Overview

RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between RF design and manufacturing layout design platforms. Overcoming cross-platform interoperability issues shortens turnaround times

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