On-Device Tensilica AI Platform For AI SoCs

On-Device Tensilica AI Platform For AI SoCs
by Kalar Rajendiran on 10-05-2021 at 6:00 am

Varying On Device AI Requirements 1

During his keynote address at the CadenceLIVE 2021 conference, CEO Lip-Bu Tan made some market trend comments. He observed that most of the data nowadays is generated at the edge but only 20% is processed there. He predicted that by 2030, 80% of data is expected to be processed at the edge. And most of this 80% will be processed on edge… Read More


Accelerating Exhaustive and Complete Verification of RISC-V Processors

Accelerating Exhaustive and Complete Verification of RISC-V Processors
by Ashish Darbari on 08-29-2021 at 6:00 am

FIG 1 spec bug

As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More


A PI Engineer’s Guide to Up-Leveled Signoff Methodology

A PI Engineer’s Guide to Up-Leveled Signoff Methodology
by Admin on 08-26-2021 at 12:00 am

August 26, 2021

Overview

Power integrity (PI) engineers have been running Cadence®Sigrity™ tools to perform DC, AC, and power-ripple analysis for decades.  Sigrity X technology is recognized by the industry as simply the best to ensure that sufficient, efficient, and stable power is delivered to the components in your design.  

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Cadence Tempus Update Promises to Transform Timing Signoff User Experience

Cadence Tempus Update Promises to Transform Timing Signoff User Experience
by Tom Simon on 08-23-2021 at 6:00 am

Tempus With SmartHub for Timing Signoff

Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More


A Signal Integrity Engineer’s Guide to Successful GDDR6 Design

A Signal Integrity Engineer’s Guide to Successful GDDR6 Design
by Admin on 08-19-2021 at 12:00 am

August 19, 2021

Overview

As a supplier of GDDR6 design IP for memory controllers, Cadence has a holistic solution of design and analysis tools that implement and simulate the IP in the chip as well as interconnect in the IC package and PCB. The high-performing GDDR6 memory interface is essential to graphics cards, game consoles,

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Boost Verification Productivity with PSS 2.0 and Perspec

Boost Verification Productivity with PSS 2.0 and Perspec
by Admin on 06-10-2021 at 12:00 am

June 10, 2021

Overview

SoC level verification and validation is often the bottleneck of chip design projects due to lack of methodology and automation for creating system level stimulus and limited content reuse. Complex system use-cases, involve interactions between different elements in the system, are hard to write, model

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