A Digital Event – November 10-11
Ready to share and discuss the latest design and verification best practices with your peers from around the world?
It’s time for our annual JasperTM User Group Conference, held on November 10 and 11 this year. This in-depth technical conference connects designers, verification engineers,… Read More
During his keynote address at the CadenceLIVE 2021 conference, CEO Lip-Bu Tan made some market trend comments. He observed that most of the data nowadays is generated at the edge but only 20% is processed there. He predicted that by 2030, 80% of data is expected to be processed at the edge. And most of this 80% will be processed on edge… Read More
As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More
Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More
Aug 17, 2021
Demands on verification teams continue to grow exponentially while time to market continues to shrink. Additionally, new classes of devices, variable software payloads, and security threats present new challenges. As teams strive to increase their verification throughput to meet these uncertainties,… Read More