WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING

WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING
by Admin on 06-17-2020 at 12:00 am

Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.

The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS

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Webinar: Advanced Methodologies to Accelerate Your Custom Layout

Webinar: Advanced Methodologies to Accelerate Your Custom Layout
by Admin on 06-10-2020 at 11:00 am

Overview

The custom layout process is a critical aspect of achieving your analog design goals in terms of performance, die area, and tapeout date.

The massive challenges of nanometer layout have led to significant innovation in EDA tools and associated methodologies. Many of these approaches are also very useful at mature nodes

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Webinar: Getting the Most Out of Your Custom Waveforms

Webinar: Getting the Most Out of Your Custom Waveforms
by Admin on 06-10-2020 at 9:00 am

Overview

Want to get more out of your current tools? Discover how to get the best out of visualizing your waveforms in the Cadence® Virtuoso® ADE Product Suite.  A detailed explanation and demo will provide something for all levels of experience with the tool.

The webinar will cover:

  • Navigating around the graph to focus on areas
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Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)

Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)
by Admin on 06-07-2020 at 2:00 pm

Overview

The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.

Topics such as physically aware logic restructuring,

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TRAINING: DESIGNING MMWAVE MIMO RADAR SYSTEMS WITH AWR SOFTWARE

TRAINING: DESIGNING MMWAVE MIMO RADAR SYSTEMS WITH AWR SOFTWARE
by Admin on 06-04-2020 at 10:00 am

Date/Time:
Thursday, June 4
10:00am PDT

Presenter: Dr. Tero Kiuru, VTT

This web presentation covers the design of a frequency-modulated continuous wave (FMCW) MIMO radar system with Cadence® AWR Design Environment® software. The purpose of the system is for short-range high-resolution localization of nearby moving objects.

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Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success

Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success
by Admin on 06-02-2020 at 11:00 am

Overview

As designs grow in complexity, rigorous formal verification is essential to meet aggressive requirements for power, performance, area, and time to market. Equivalence checking, static verification, automated ECO, and constraint design for clock domain crossing (CDC) are some of the challenges that signoff designers

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Webinar: Investigating and Improving Clock Delays

Webinar: Investigating and Improving Clock Delays
by Admin on 05-31-2020 at 2:00 pm

Overview

As typical system-on-chip designs grow larger and move to the latest FinFET process nodes, clocking constraints become ever more complex. The Cadence® Innovus™ Implementation System’s CCOpt™ useful skew optimization engine is a powerful tool to close the timing on the latest high-speed designs. Understanding and

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Webinar: What’s New in AWR Design Environment V15

Webinar: What’s New in AWR Design Environment V15
by Admin on 05-28-2020 at 4:00 pm

Overview

What’s New in AWR Design Environment V15

Cadence recently launched the AWR Design Environment® V15 version, which includes AWR® Microwave Office, AWR Visual System Simulator ™ (VSS), and AWR AXIEM® and Analyst ™ electromagnetic (EM) simulators. This new version expands the Cadence software product portfolio… Read More


Webinar: Modelling Complex System Signal Path – for Signal Integrity

Webinar: Modelling Complex System Signal Path – for Signal Integrity
by Admin on 05-28-2020 at 11:00 am

Overview 

Highly complex structures found in Rigid-flex PCBs, stacked-die IC packages, connectors and cables must be modeled accurately in 3D for structure optimization and high-speed signaling compliance. High-speed signaling, such as in 112G SerDes interfaces, relies on high-fidelity interconnect design. Any slight

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