Tag: cadence
CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff
CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff
CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML
Crack the Verification Double Trouble!
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with… Read More
CadenceTECHTALK: Static Timing Analysis and Some Important Basics
CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.
The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More
CadenceTECHTALK: Integrated Thermal Analysis for RF MMIC and PCB Power Applications
Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More
Club Formal India – 2022
Webinar: Generate the Best Mesh Every Time – Automatically
Date: Tuesday, December 13, 2022
Time: 8:00am PST | 10:00am CST | 5:00pm CET
Unstructured meshing can automate much of the mesh generation process, saving significant engineering time and cost. However, controlling numerical errors resulting from the discrete mesh requires adaptation to the developing solution. Cadence … Read More