Overview
Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.
Addressing these concerns through simulation during system planning and continuing through signoff will accelerate… Read More
DesignCon 2022 is back to a live conference, from Tuesday, April 5th through Thursday, April 7th, at the Santa Clara Convention Center.
DesignCon is a unique gathering in our industry. Its roots incorporated a focus on complex design and analysis requirements of (long-reach) high-speed interfaces. Technical… Read More
Overview
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis also is extremely… Read More
Dan is joined by Jeff Critten, VP of sales at Corigine. They discuss the unique capabilities of Corigine that allows support of both emulation and prototyping in one platform.
Jeff Critten has been in the EDA industy for over 25yrs. He started with Cadence as a verification AE in 1997 and moved into a sales role where he was promoted… Read More
Increase both performance and capacity for chip, interposer, package, and PCB using Clarity 2022.1
Overview
The Cadence® Clarity™ 3D Solver, utilized by scores of customers across the globe, continues to accelerate design flows for leading companies in industries such as medical, hyperscale computing, 5G, automotive, and
Overview
As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. With these complex designs, designers will require automation to overcome the limits of using expert… Read More
Ever since the cost of development started growing exponentially, engineering teams have been deploying a shift-left strategy to software development and system verification. While this has helped contain cost and accelerated product development schedules, a shift-left strategy is not without challenges. A virtual platform… Read More
March 9, 2022
Overview
System planning is a major part of the multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving
08 Mar 2022
Online
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow?
Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar.
Built on a multi-threaded frame-based architecture, the Cadence
Exciting times for the semiconductor industry! Last week Intel announced a billion dollar fund to build a foundry ecosystem and today Intel announced they are acquiring foundry Tower Semiconductor for $5.6 billion dollars, WOW! Some people doubted Intel’s commitment to the foundry market this time. I think we can now put that… Read More
