Tag: cadence

CadenceLIVE Americas 2021 A Digital Event

CadenceLIVE Americas 2021 A Digital Event
by Admin on 06-08-2021 at 12:00 am

June 8-9

For the last seventeen years, CadenceLIVE has brought together technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity. Join us for two days of exciting keynotes and, interesting user presentations, and connect with us and our partners and sponsors… Read More

Accelerate Full-Chip Signoff with Massively Parallel Scalability

Accelerate Full-Chip Signoff with Massively Parallel Scalability
by Admin on 06-01-2021 at 12:00 am

Overview

Physical design constraints become a lot more complicated in the advanced nodes, leading to the exponential growth of design rules while adding complexity. Decreasing the active device sizes and higher geometry densities results in increased design rule check (DRC) run time, a big metal fill impact on chip functionality,

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Thermal and Stress Analysis of 3D-ICs with Celsius Thermal Solver

Thermal and Stress Analysis of 3D-ICs with Celsius Thermal Solver
by Admin on 06-01-2021 at 12:00 am

Overview

Join us to fully understand the thermal and stress challenges introduced by 3D-ICs, which are cross-fabric problems.  Learn how the Cadence Celsius™ Thermal Solver helps you solve this problem by producing thermal gradient for the whole system, enabling analysis from early design to signoff​.

Takeaways:

  • Seamless
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Accelerate DFT Simulations with Xcelium Multi-Core Technology

Accelerate DFT Simulations with Xcelium Multi-Core Technology
by Admin on 05-26-2021 at 12:00 am

Overview

High-performance DFT simulation is key to completing today’s complex systems on chip (SoCs) on schedule. Because most simulators were developed before the multi-core era, they process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in

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What’s the Recipe for Efficient Analog IC Design and Verification?

What’s the Recipe for Efficient Analog IC Design and Verification?
by Admin on 05-19-2021 at 12:00 am

Overview

For analog IC designers, the most important capability is rapid simulation of an accurate model of their circuits. Early in the design process, they explore architectures and novel approaches and need an agile simulation flow that gives them confidence that the implemented design is capable of meeting the system specs.

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Novel Metrics Visualisation for Quick Design Analysis

Novel Metrics Visualisation for Quick Design Analysis
by Admin on 05-18-2021 at 12:00 am

Overview

Creating a final design is a sequence of operations from register-transfer-level (RTL) synthesis, through implementation to signoff. Each of these operations is further split into different steps, such as placement, clock tree synthesis, and routing. When run as part of a typical design flow, these steps generate

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CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA

CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA
by Admin on 04-20-2021 at 12:00 am

Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.

CadenceCONNECT:

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How Mentor became Siemens EDA

How Mentor became Siemens EDA
by Daniel Nenni on 04-05-2021 at 6:00 am
Categories: EDA
7 Comments

Messy dog food

When I started in EDA the big three were Daisy, Mentor and Valid (DMV as we called them). Then came Synopsys in 1986 followed by Cadence, which was a clever merger between ECAD (Dracula DRC) and Solomon Design. Daisy and Valid were pushed aside and then there were, “Three dogs hovering over one bowl of dog food, not a pretty site.”… Read More

Hierarchical PI Analysis of Large Designs with Voltus Solution

Hierarchical PI Analysis of Large Designs with Voltus Solution
by Admin on 03-11-2021 at 12:00 am

Hierarchical PI Analysis of Large Designs with Voltus Solution

Memory requirements and runtime for full chip EMIR analysis has become a major challenge at advanced nodes as it is not uncommon to see designs with 100s of millions of cells and some even in the multi-billion range. To run a flat analysis requires multiple terabytes

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