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USB4 Makes Interfacing Easy, But is Hard to Implement

USB4 Makes Interfacing Easy, But is Hard to Implement
by Tom Simon on 03-02-2021 at 10:00 am

USB made its big splash by unifying numerous connections into a single cable and interface. At the time there were keyboard ports, mouse ports, printer ports and many others. Over the years USB has delivered improved performance and greater functionality. However, as serial interfaces became more popular and started being used for what were previously parallel interfaces, there was a proliferation of new serial cables and protocols. The latest version of USB, referred to as USB4, makes a new bold move to unify many of these different interfaces. USB4 naturally works for USB data streams, but it also can tunnel PCIe, Thunderbolt3, and DisplayPort data streams.

USB4 supports 20 Gbps and can go up to 40 Gbps. It specifies use of the USB Type-C connector, which further simplifies the user experience. And unlike its predecessors, it mandatorily manages the power distribution with USB PD. It offers one connector for device interfaces, storage, peripherals and display output. However, with this unification comes complexity under the hood. Many legacy and new features are included in the host and device specification for USB4.

One of the hallmarks of the USB interface is its backward compatibility. And so, USB4 is USB 2 and USB 3 compatible, as one might expect. USB4 is a multi-lane interface, with lane bonding support as well for pipelining. Higher data rates call for more sophisticated encoding and error correction algorithms. Layers of abstraction for routing and tunneling have added complexity. Indeed, the list of features inside a properly functioning USB4 interface is lengthy.

Implementing USB4 is not a trivial task. At each stage of development, it is essential to have the ability to verify that everything conforms to the specification and is implemented properly. It is imperative to have a verification environment that can exercise all the functionality and provide designers information to help isolate and pin down issues. Last Summer Truechip, a leading provider of verification IP (VIP), announced the customer shipment of their USB4 and eUSB VIP.

USB4 Verification IP
USB4 Verification IP

Truechip has a truly impressive offering of VIP for nearly every category of design. These include storage, BUS & interfaces, USB, automotive, memory, PCIe, networking, MIPI, AMBA, display, RISC-V, and defense & avionics. Their VIP includes coverage, assertions, BFMs, monitors, scoreboard and testcases. The host and device BFM models, includes bus functional models and agents for the electrical layer, logical layer, transport layer, configuration layer and the protocol adapter layer. Their VIP works on a wide range of platforms – UVM, OVM, VMM and Verilog.

Truechip’s USB4 VIP is fully compliant with the v1.0 specification. It includes backward compatibility with USB 2.0. As expected, it also includes the Power Delivery for USB 3.0 and Type-C v2.0. Truchip’s VIP also supports all logical layer ordered sets. It has 64/66b, 128/132b and Reed-Solomon FEC encoding and decoding. In reality the list of features it supports is too long to list here.

The deliverables for the USB4 VIP are also comprehensive. In addition to the host and device models, it includes bus functional models and agents for the electrical layer, logical layer, transport layer, configuration layer and the protocol adapter layer. It comes with a monitor and scoreboard. There are test suites for basic and directed protocol tests. It has low power tests, error scenario tests, stress tests, random tests and compliance tests.

Truechip’s USB4 VIP is highly configurable and contains everything needed to verify any portion of a USB4 interface design. With it designers can be assured that their finished products will fully conform to the specification and will work reliably in silicon. For more information on this VIP check out the Truechip website.

Also read:

Bringing PCIe Gen 6 Devices to Market

PCIe Gen 6 Verification IP Speeds Up Chip Development

TrueChip CXL Verification IP

Webinar Replay on TileLink from Truechip

 

 

 

 

 

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