Power integrity analysis in large chip designs is especially challenging thanks to the huge dynamic range the analysis must span. At one end, EM estimation and IR drop through interconnect and advanced transistor structures require circuit-level insight—very fine-grained insight but across a huge design. At the other, activity modeling requires system-level insight and rolling EM-IR analytics up to the full-chip power delivery network (PDN). Watch this CadenceTECHTALK on hierarchical PI analysis March 11 on a new approach to meet this need. REGISTER NOW to make sure you don’t miss the webinar.
These are real design problems today, such as in the giant AI chips you are likely to see in hyperscalar installations, or perhaps in a CPU cluster together with eight giant GPUs. These are already way too big to run full-flat EM-IR analysis across the whole chip. Yet they are very important analyses to get right, because marketable implementations depend on finding the narrow window between under-design and over-design, between a design that may fail on timing and/or reliability in production or a design that you didn’t sufficiently size up critical areas of the PDN, or a design for which, to overcompensate for an uncertain analysis, you sized up too much of the network, pushing chip area outside a profitable bound.
Cadence has introduced a hierarchical analysis methodology in the Voltus IC Power Integrity Solution, which is particularly well suited to large designs with multiple repeated elements like those GPUs. (Come to think of it, this may well cover most super-large designs. After all, who is going to build such a design purely out of unique functions?) This latest release will generate models for IP blocks that can stand in for those blocks in full-chip analysis. These models have an order-of-magnitude-lower memory demand yet preserve accuracy within a few percent of a full-flat analysis—a very practical approach to managing EM-IR analysis across huge designs.
Memory requirements and runtime for full-chip EM-IR analysis has become a major challenge at advanced nodes. It is not uncommon to see designs with 100s of millions of cells and some even in the multi-billion range. To run a flat analysis requires multiple terabytes of memory over a distributed network. To mitigate these issues, the Cadence® Voltus™ IC Power Integrity Solution enables designers to run hierarchical analysis using IP modeling technology. This helps designers create xPGV models for their IP blocks, accurately capturing the demand current and electrical parasitics. These xPGV models are an order of magnitude smaller compared to the fully extracted block. When used in the chip-level analysis, can help significantly reduce runtime and memory. The modeling methodology used in the Voltus IC Power Integrity Solution ensures minimal result difference relative to a fully flat analysis. This TechTalk will cover the generation of xPGV models, including the package model, and their use in IC-level analysis.
Attend this CadenceTECHTALK to learn how to:
- Run your largest designs much faster with lower memory
- Perform very accurate sub-chip analysis, including impact of chip-level demand current and parasitics
- Reuse IP models in different designs or for multiple instantiations within a design
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