Is AI-Based RTL Generation Ready for Prime Time?

Is AI-Based RTL Generation Ready for Prime Time?
by Bernard Murphy on 10-02-2024 at 6:00 am

shutterstock 2495413145 min

In semiconductor design there has been much fascination around the idea of using large language models (LLMs) for RTL generation; CoPilot provides one example. Based on a Google Scholar scan, a little over 100 papers were published in 2023, jumping to 310 papers in 2024. This is not surprising. If it works, automating design creation… Read More


Safety Grading in DNNs. Innovation in Verification

Safety Grading in DNNs. Innovation in Verification
by Bernard Murphy on 09-25-2024 at 6:00 am

Innovation New

How do you measure safety for a DNN? There is no obvious way to screen for a subset of safety-critical nodes in the systolic array at the heart of DNNs. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More


Bird’s Eye View Magic: Cadence Tensilica Product Group Pulls Back the Curtain

Bird’s Eye View Magic: Cadence Tensilica Product Group Pulls Back the Curtain
by Bernard Murphy on 09-18-2024 at 6:00 am

car 5 copy small

Even for experienced technologists some technologies can seem almost indistinguishable from magic. One example is the bird’s eye camera view available on your car’s infotainment screen. This view appears to be taken from a camera hovering tens of feet above your car. As an aid to parallel parking, it’s a brilliant invention; … Read More


Bluetooth 6.0 Channel Sounding is Here

Bluetooth 6.0 Channel Sounding is Here
by Bernard Murphy on 09-11-2024 at 6:00 am

car keyless entry

I posted a blog on this topic a year ago. Now the Bluetooth Sig has (just) ratified the standard it is timely to provide a reminder on what this new capability can offer. Channel Sounding introduced in Bluetooth Core specification version 6.0 is a method to significantly increase the accuracy of Bluetooth-based distance measurements,… Read More


Bug Hunting in NoCs. Innovation in Verification

Bug Hunting in NoCs. Innovation in Verification
by Bernard Murphy on 08-28-2024 at 6:00 am

Innovation New

Despite NoCs being finely tuned in legacy subsystems, when subsystems are connected in larger designs or even across multi-die structures, differing traffic policies and system-level delays between NoCs can introduce new opportunities for deadlocks, livelocks and other hazards. Paul Cunningham (GM, Verification at Cadence),… Read More


The Future of Logic Equivalence Checking

The Future of Logic Equivalence Checking
by Bernard Murphy on 08-07-2024 at 6:00 am

LEC concept

Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More


Theorem Proving for Multipliers. Innovation in Verification

Theorem Proving for Multipliers. Innovation in Verification
by Bernard Murphy on 07-31-2024 at 6:00 am

Innovation New

An explosion in multiplier types/combinations lacking well-established C reference models for equivalence checking is prompting a closer look at theorem proving methods for verification. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco… Read More


A New Class of Accelerator Debuts

A New Class of Accelerator Debuts
by Bernard Murphy on 07-22-2024 at 6:00 am

Chimera GPNPU Block diagram

I generally like to start my blogs with an application-centric viewpoint; what end-application is going to become faster, lower power or whatever because of this innovation? But sometimes an announcement defies such an easy classification because it is broadly useful. That’s the case for a recent release from Quadric, based… Read More


Accelerating Analog Signoff with Parasitics

Accelerating Analog Signoff with Parasitics
by Bernard Murphy on 07-17-2024 at 6:00 am

Quantus Insight min

An under-appreciated but critical component in signing off the final stage of chip design for manufacture is timing closure – aligning accurate timing based on final physical implementation with the product specification. Between advanced manufacturing processes and growing design sizes, the most important factors determining… Read More


Production AI is Taking Off But Not Where You Think

Production AI is Taking Off But Not Where You Think
by Bernard Murphy on 07-10-2024 at 6:00 am

TinyML

AI for revolutionary business applications grabs all the headlines but real near-term growth is already happening, in consumer devices and in IoT. For good reason. These applications may be less eye-catching but are eminently practical: background noise cancellation in earbuds and hearing aids, keyword and command ID in voice… Read More