Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio

Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio
by Bernard Murphy on 04-14-2021 at 6:00 am

Siemens Hardware assisted Verification platform launch graphic 2 32521 min

Siemens EDA’s Veloce emulation products are long-established and worthy contenders in any emulation smack-down. But there was always a hole in the complete acceleration story. Where was the FPGA prototyper? Current practice requires emulation for fast simulation with hardware debug, plus prototyping for faster simulation… Read More


Cadence Dynamic Duo Upgrade Debuts

Cadence Dynamic Duo Upgrade Debuts
by Bernard Murphy on 04-08-2021 at 6:00 am

Dynamic Duo min

Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware… Read More


VC Formal SIG Virtually Conferences in Europe

VC Formal SIG Virtually Conferences in Europe
by Bernard Murphy on 04-06-2021 at 6:00 am

VC Formal graphic min

Pratik Mahajan, Synopsys VC Formal R&D Group Director, kicked off an absorbing event featuring talks from multiple customers in Europe. He spent some time on formal signoff, an important topic that I’m still not sure is fully understood. Answering the questions “OK, we did a bunch of formal checking but how does that affect… Read More


Formal for Post-Silicon Bug Hunting? Makes perfect sense

Formal for Post-Silicon Bug Hunting? Makes perfect sense
by Bernard Murphy on 03-31-2021 at 6:00 am

Bug hunting process for DDR problem min

You verified your product design against every scenario your team could imagine. Simulated, emulated, with constrained random to push coverage as high as possible. Maybe you even added virtualized testing against realistic external traffic. You tape out, wait with fingers crossed for first silicon to come back. Plug it into… Read More


Reducing Compile Time in Emulation. Innovation in Verification

Reducing Compile Time in Emulation. Innovation in Verification
by Bernard Murphy on 03-25-2021 at 6:00 am

Innovation image 2021

Is there a way to reduce cycle time in mapping large SoCs to an FPGA-based emulator? Paul Cunningham (GM, Verification at Cadence), Jim Hogan (RIP) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Improving FPGA-Based Logic Emulation Systems through Machine LearningRead More


SoC Integration – Predictable, Repeatable, Scalable

SoC Integration – Predictable, Repeatable, Scalable
by Bernard Murphy on 03-24-2021 at 6:00 am

IPDD SIPD stack min

On its face System-on-chip (SoC) integration doesn’t seem so hard. You gather and configure all the intellectual properties (IPs) you’re going to need, then stitch them together. Something you could delegate to new college hires, maybe? But it isn’t that simple. What makes SoC integration challenging is that there are so many… Read More


RIP Jim Hogan – An Industry Icon

RIP Jim Hogan – An Industry Icon
by Bernard Murphy on 03-21-2021 at 8:00 am

RIP Jim Hogan

An unavoidable consequence of getting older is that more frequently our friends and colleagues unexpectedly leave us for their final venture. Jim Hogan, widely known and loved in the semiconductor industry, has passed on. He will leave a substantial hole in the hearts of many. Always ready with seasoned advice, a sympathetic … Read More


Quantum Tunneling for OTPs, PUFs: Higher security

Quantum Tunneling for OTPs, PUFs: Higher security
by Bernard Murphy on 03-17-2021 at 6:00 am

ememory neofuse min

I’ve had a number of enjoyable discussions with John East who ran Actel until it was acquired. (John and Actel devices also play an important role in my book, The Tell-Tale Entrepreneur.) This is relevant because Actel were well-known for their anti-fuse FPGAs. eMemory Technology, the subject of this blog, also produce an anti-fuse… Read More


Cadence Underlines Verification Throughput at DVCon

Cadence Underlines Verification Throughput at DVCon
by Bernard Murphy on 03-10-2021 at 6:00 am

Verification Throughput min

Paul Cunningham, CVP and GM of the System Verification Group at Cadence gave the afternoon Keynote on Tuesday at DVCon and doubled down on his verification-throughput message. At the end of the day, what matters most to us in verification is the number of bugs found and fixed per dollar per day. You can’t really argue with that message.… Read More


TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution

TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution
by Bernard Murphy on 03-03-2021 at 6:00 am

voltus min

Power integrity analysis in large chip designs is especially challenging thanks to the huge dynamic range the analysis must span. At one end, EM estimation and IR drop through interconnect and advanced transistor structures require circuit-level insight—very fine-grained insight but across a huge design. At the other, activity… Read More