Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I launched our series on Innovation in Verification at the beginning of last year. We wanted to explore basic innovations and new directions researchers are taking for hardware and system verification. Even we were surprised to find how rich a seam we had tapped. We plan… Read More
Author: Bernard Murphy
2020 Retrospective. Innovation in Verification
CDC, Low Power Verification. Mentor and Cypress Perspective
Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More
ESL Expertise when You Need It. Spinning Up Faster
System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different… Read More
The Heart of Trust in the Cloud. Hardware Security IP
You might think that cloud services run on never-ending racks of servers and switches in giant datacenters. But what they really run on is trust. Trust that your data (or your client’s data) is absolutely tamper-proof inside that datacenter. Significantly more secure than it would be if you tried to manage the same operations in… Read More
An Accellera Update. COVID Accelerates Progress
Normally I would post this Accellera update during DVCon US but, no surprise, this year is weird. Particularly in conferences going virtual. The last DVCon was in early March of this year, right on the cusp of the shutdown. I was there in person, as was Lu Dai (Chairman of Accellera). Both Synopsys and Cadence had dropped out, citing… Read More
More on Bug Localization. Innovation in Verification
Mining assertions from constrained random simulations to localize bugs. Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Feel free to comment.
The Innovation
This month’s pick is Symptomatic bug localization for functional debug of hardware designs. This paper was presented… Read More
Smoother MATLAB to HLS Flow
It hard to imagine design of a complex signal processing or computer vision application starting somewhere other than in MATLAB. Prove out the algorithm in MATLAB, then re-model in Simulink, to move closer to hardware. First probably an architectural model, using MATLAB library functions to prove out behavior of the larger system.… Read More
ML plus formal for analog. Innovation in Verification
Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.
The Innovation
This month’s pick… Read More
Folding at Home. The Ultimate in Parallel Acceleration
You may have heard of Folding at Home. It’s a very creative way that a bioengineering team, based at Washington University in St Louis, are modeling the process of protein folding. Greg Bowman, an associate professor of biochemistry and biophysics at the university directs the project and presented at Arm DevSummit this year. … Read More
The Reality of ISO 26262 Interpretation. Experience Matters
Interpreting ISO 26262 without ambiguity is not always easy. Suppliers and integrators can read some aspects differently, creating confusion. Which is a problem since ISO 26262 has become so much a part of any discussion on automotive electronics that it has gained almost biblical significance. Yet most of us, even suppliers… Read More
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Podcast EP3: Tomorrow’s Semiconductors with Jim Hogan