Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task… Read More
Author: Bernard Murphy
Coverage Analysis in Questa Visualizer
NoC-Based SoC Design. A Sondrel Perspective
Why are NoCs important in modern SoCs and what are best design practices for using NoC? As always, a great place to start is the perspective of an SoC design organization which depends on pumping out high performance designs. Sondrel is a turnkey ASIC service provider, covering the spectrum from system design to silicon supply. … Read More
Formal at System Level. Innovation in Verification
Formal verification at the SoC level has long seemed an unapproachable requirement. Maybe we should change our approach. Could formal be practical on a suitable abstraction of the SoC? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and… Read More
DSPs in Radar Imaging. The Other Compute Platform
In the flood of CPU and GPU announcements in pursuit of new technology advances, it is easy to lose track of another kind of platform – DSPs. Digital signal processors, once a niche platform for specialized applications, are now front and center in some of the hottest technologies. Because their strength in signal processing has… Read More
Arm Aims at Mobile Gaming
Clearly unfazed by the collapse of the proposed merger with Nvidia, Arm just announced products in support of, what else, mobile gaming. Nvidia turf. Of course Nvidia’s gaming strength is in tethered platforms or laptops. However, understand that 50% of video gaming revenue in 2020 came from smartphone games and that growth is… Read More
Intelligently Optimizing Constrained Random
“Who guards the guardians?” This is a question from Roman times which occurred to me as relevant to this topic. We use constrained random to get better coverage in simulation. But what ensures that our constrained random testbenches are not wanting, maybe over constrained or deficient in other ways? If we are improving with a faulty… Read More
CXL Verification. A Siemens EDA Perspective
Amid the alphabet soup of inter-die/chip coherent access protocols, CXL is gaining a lot of traction. Originally proposed by Intel for cross-board and cross-backplane connectivity to accelerators of various types (GPU, AI, warm storage, etc.), a who’s who of systems and chip companies now sits on the board, joined by an equally… Read More
Accellera Update: CDC, Safety and AMS
I recently had an update from Lu Dai, Chairman of Accellera, also Sr. Director of Engineering at Qualcomm. He’s always a pleasure to talk to, in this instance giving me a capsule summary of status in 3 areas that interested me: CDC, Functional Safety and AMS. I will start with CDC, a new proposed working group in Accellera. To manage… Read More
5G for IoT Gets Closer
Very recently, 3GPP announced that 5G Release 17 was finalized. One important consequence is that 5G RedCap (reduced capacity) is now real and that means 5G becomes accessible to IoT devices. Think smart wearables (e.g. watches), industrial sensors and surveillance devices. “So what?”, you protest. “I don’t need 5G on my watch.… Read More
Stalling to Uncover Timing Bugs. Innovation in Verification
Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More
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Podcast EP100: A Look Back and a Look Ahead with Dan and Mike