A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design
by Mike Gianfagna on 12-04-2024 at 6:00 am

A Master Class with Ansys and Synopsys, The Latest Advances in Multi Die Design

2.5D and 3D multi-die design is rapidly moving into the mainstream for many applications. HPC, GPU, mobile, and AI/ML are application areas that have seen real benefits. The concept of “mix/match” for chips and chiplets to form a complex system sounds deceptively simple. In fact, the implementation and analysis techniques required… Read More


Webinar: Accelerating System Design Creation with Integrated Analysis

Webinar: Accelerating System Design Creation with Integrated Analysis
by Admin on 11-13-2024 at 12:08 am

With the EE Cockpit in Allegro X System Capture, electrical engineers can run analyses during the schematic design phase without needing complicated analysis setups or specialized models to get meaningful results. With in-design analysis, they can provide accurate constraints to the PCB designer and verify that these constraints… Read More


How AI is Redefining Data Center Infrastructure: Key Innovations for the Future

How AI is Redefining Data Center Infrastructure: Key Innovations for the Future
by Kalar Rajendiran on 10-10-2024 at 10:00 am

Connectivity Demands for AI Alphawave Semi

Artificial intelligence (AI) is driving a transformation in data center infrastructure, necessitating cutting-edge technologies to meet the growing demands of AI workloads. As AI systems scale up and out, next-gen compute servers, switches, optical-electrical links, and flexible, redundant networking solutions are … Read More


Advanced EM simulations target conducted EMI and transients

Advanced EM simulations target conducted EMI and transients
by Don Dingee on 09-19-2022 at 6:00 am

Advanced EM simulations yield both conducted and radiated EMI in automotive power integrity analysis

A vital benefit of advanced EM simulations is their ability to take on complicated physical test setups, substituting far easier virtual tests yielding accurate results earlier during design activities. The latest release of Keysight PathWave ADS 2023 continues speeding up engineering workflows. Let’s look at three… Read More


A MasterClass in Signal Path Design with Samtec’s Scott McMorrow

A MasterClass in Signal Path Design with Samtec’s Scott McMorrow
by Mike Gianfagna on 04-25-2022 at 10:00 am

Samtec Flyover Technology

We all know signal integrity and power integrity are becoming more important for advanced design. Like package engineering, the obscure and highly technical art of SI/PI optimization has taken center stage in the design process. And the folks who command expertise in these areas have become the rock stars of the design team. I … Read More


WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama

WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama
by Don Dingee on 02-01-2022 at 6:00 am

Flat Z design and voltage ripple example in board-level EM simulation

Advanced board designs are fertile ground for misbehavior in time and frequency domains. Relying on intuition, then waiting until near-final product for power integrity (PI) or EMI testing almost guarantees board respins are coming. Lumped-parameter simulations of on-board power delivery networks (PDNs) struggle with … Read More


Samtec Keynote – Power Integrity is the New Black Magic

Samtec Keynote – Power Integrity is the New Black Magic
by Mike Gianfagna on 05-10-2021 at 6:00 am

Samtec Keynote – Power Integrity is the New Black Magic

The Signal Integrity Journal recently held a half day Electronic Systems SI/PI Forum that included presentations from industry leaders covering key design topics for signal integrity and power integrity engineers. The event was sponsored by Cadence. The keynote for the event was presented by Istvan Novak, principal signal… Read More


TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution

TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution
by Bernard Murphy on 03-03-2021 at 6:00 am

voltus min

Power integrity analysis in large chip designs is especially challenging thanks to the huge dynamic range the analysis must span. At one end, EM estimation and IR drop through interconnect and advanced transistor structures require circuit-level insight—very fine-grained insight but across a huge design. At the other, activity… Read More


Cadence Defines a New Signoff Paradigm with Tempus PI

Cadence Defines a New Signoff Paradigm with Tempus PI
by Mike Gianfagna on 07-20-2020 at 10:00 am

Screen Shot 2020 06 24 at 11.24.34 PM

Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More


Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
by Mike Gianfagna on 03-24-2020 at 10:00 am

Screen Shot 2020 03 14 at 5.36.37 PM

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More