Chiplets have been trending on SemiWiki for the past two years and I think that will continue into the distant future. As a potential way to unclog Moore’s Law, you can bet the semiconductor ecosystem will prove once again to be a chiplet force of nature driving semiconductor company roadmaps to smaller and better things.
To be clear, the chiplet concept is not new. We have been doing multi chip modules (MCMs) for years now. IP blocks are also not new and that is what a chiplet is, a hard IP block. What’s new is the chiplet ecosystem that is developing so all companies, big and small, can design with chiplets.
To allow chiplet connectivity we have the developing Universal Chiplet Interconnect Express standard. UCIe is an open specification for a die-to die interconnect and serial bus between chiplets. It’s co-developed by our colleagues at AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.
One of the critical pieces of the chiplet UCIe design puzzle of course is verification, which brings us to a recent announcement:
Speaking at SemIsrael expo 2022 Nitin Kishore, CEO, Truechip, said, “UCIe is the need of the hour as it not only assists to increase yield for SoCs with larger die size but also allows to intermix components (or chiplets) from multiple vendors within a single package. SoC providers can reduce time to market and cost if they can re-use chiplets from previous or other chips (like a processor subsystem or a memory subsystem, etc.) versions or plug-in chiplets from third-party vendors. With the launch of the UCIe Verification IP, I believe that this protocol will enable design houses to configure, launch, analyze, manage sustainability targets, and accelerate them achieve their design goals.”
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of various Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment.
Nitin concluded, “With high-speed support of 32GTps per lane and the fact that it can also enable the mapping of other protocols via the streaming mode, UCIe is not only a high-performance protocol but also an interconnect protocol that requires very low power. The advantages of UCIe makes it the most innovative technique to smoothen the way towards a truly open multi-die system ecosystem by ensuring interoperability.”
Intellectual Property is a critical part of the semiconductor ecosystem. In fact, without the commercial IP market the fabless semiconductor business would not be what it is today. IP is still the most read topic on SemiWiki and the fastest growing semiconductor design market segment and will continue to be so, with or without chiplets. With chiplets, however, the IP market could easily hit the $10B mark by the end of the decade, absolutely.
Truechip is a leading provider of Verification IPs, NOC Silicon IP, GUI based automation products and chip design services, which aid to accelerate IP/ SOC design thus lowering the cost and the risks associated with the development of ASIC, FPGA and SOC. Truechip provides Verification IP solutions for RISC V-based chips, Networking, Automotive, Microcontroller, Mobile, Storage, Data Centers, AI domains for all known protocols along with custom VIP development. The company has global footprints and coverage across North America, Europe, Israel, Taiwan, South Korea, Japan, Vietnam and India. Truechip offers Industry’s first 24 x 7 technical support.