Webinar: The UCIe™ 1.1 Specification: Future Applications of Chiplets

Webinar: The UCIe™ 1.1 Specification: Future Applications of Chiplets
by Admin on 09-25-2023 at 3:05 pm

The UCIe™ 1.1 Specification: Future Applications of Chiplets
Thursday, October 12, 2023 
10 AM PT / 1 PM ET

Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel 

The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification

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Podcast EP179: An Expert Panel Discussion on the Move to Chiplets

Podcast EP179: An Expert Panel Discussion on the Move to Chiplets
by Daniel Nenni on 09-01-2023 at 10:00 am

Dan is joined by a panel of experts to discuss chiplets and 2.5/3D design. The panelists are: Saif Alam – Vice President of Engineering at Movellus Inc., Tony Mastroianni Siemens EDA- Advanced Packaging Solutions Director and Craig Bishop – CTO Deca Technologies.

In this spirited and informative discussion the … Read More


CadenceTECHTALK: Proactively Address Thermal Concerns in Advanced IC Packages

CadenceTECHTALK: Proactively Address Thermal Concerns in Advanced IC Packages
by Admin on 08-31-2023 at 2:42 pm

Date: Thursday, October 12, 2023

Time: 10:00am – 11:00am (PDT)

The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages… Read More


WEBINAR: The Power of Formal Verification: From flops to billion-gate designs

WEBINAR: The Power of Formal Verification: From flops to billion-gate designs
by Daniel Nenni on 08-15-2023 at 5:00 pm

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Semiconductor industry is going through an unprecedented technological revolution with AI/ML, GPU, RISC-V, chiplets, automotive and 5G driving the hardware design innovation. The race to deliver high performance, optimizing power and area (PPA), while ensuring safety and security is truly on. It has never been a more excitingRead More


CEO Interview: Harry Peterson of Siloxit

CEO Interview: Harry Peterson of Siloxit
by Daniel Nenni on 08-04-2023 at 6:00 am

hwp photo

Harry Peterson is a mixed-signal chip designer with a BS in Physics from Caltech.  He managed IC design groups within Fairchild, Kodak, Philips, Northern Telecom, Toshiba and Pixelworks.  During sabbaticals he helped fly experiments on NASA’s orbiting satellite observatory (OSO-8) and build telescopes in the Canary… Read More


SEMICON West 2023 Summary – No recovery in sight – Next Year?

SEMICON West 2023 Summary – No recovery in sight – Next Year?
by Robert Maire on 07-15-2023 at 6:00 am

Semicon west 2023

-SEMICON well attended but bouncing along the biz bottom
-Recovery seems at least a year away with memory even more
-AI creates hope but not impactful- Disconnect tween stocks & reality
-AMAT me too platform- Back end benefits from chiplets

SEMICON busy but subdued

SEMICON is certainly back to pre-covid levels or perhaps better.… Read More


Cadence TECHTALK: Solution for 3D-IC Interposer Signal Integrity

Cadence TECHTALK: Solution for 3D-IC Interposer Signal Integrity
by Admin on 07-12-2023 at 3:31 pm

Date: Wednesday, July 26, 2023

Time: 10:00am PDT | 1:00pm EDT

3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design… Read More


Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges
by Nanette Collins on 06-22-2023 at 10:00 am

CEO Outlook #2

Chances are anyone who attended the CEO Outlook will say it was an engaging, entertaining and enlightening view of the chip design space, though CEO Outlook may be a misnomer as four of the seven panelists had C-Suite titles other than CEO.

Regardless, the collective view was optimistic, though caution prevailed as the economic… Read More


Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint
by Kalar Rajendiran on 06-20-2023 at 6:00 am

Synopsys Samsung silicon wafer

Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments… Read More


Requirements for Multi-Die System Success

Requirements for Multi-Die System Success
by Daniel Nenni on 06-16-2023 at 6:00 am

Synopsys Chiplet Report 2023

Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.

As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about.

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