TSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, address the same strategic problem: integrating increasingly large, heterogeneous chiplet systems. However, they attack different physical constraints. CoPoS is an emerging panel-level … Read More
Tag: chiplets
DAC 2026: Join Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification.
Accellera Systems Initiative invites the design and verification community to join us at the 2026 Design Automation Conference for a focused technical luncheon, “Embracing AI for Advanced Design and Verification,” on Tuesday, July 28, from 12:30–1:45 p.m. at the Long Beach Convention Center, Meeting Room 104C.
Artificial… Read More
The Packaging PDK Is the Missing Layer for Co-Packaged Optics
From Photonic Device Design to Electro-Optical Realization
Co-packaged optics will not scale through photonic device performance alone.
As AI infrastructure pushes bandwidth, power, latency, and reach to new limits, optics is moving closer to the compute engine. The industry is no longer asking only whether a photonic device… Read More
AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoption
Systems-in-package (SIPs) with 2.5D and 3D heterogenous integration, consisting of multiple dies and chiplets deliver 10x more functionality than traditional monolithic chips. This capability enables innovative solutions for diverse needs in scientific computing, automotive, edge computing, and aerospace/defense.… Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and… Read More
What Winemakers and Chip Designers Have in Common
Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem,… Read More
Silicon Catalyst and Microelectronics US 2026
The designation of Silicon Catalyst as the exclusive strategic partner for Microelectronics US 2026 represents a significant alignment between a leading semiconductor startup ecosystem and a rapidly growing U.S. microelectronics industry event. This partnership reflects broader trends in semiconductor innovation, … Read More
TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation
One of my favorite times of the year is coming (sailing season) and my favorite event of the year is coming as the company I most respect will host the best international semiconductor networking event starting here in Silicon Valley.
The 32nd annual TSMC Technology Symposium represents one of the most influential events in the … Read More
Podcast EP335: The Far Reaching Impact of UCIe with Dr. Debendra Das Sharma
Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More
MZ Technologies Launches Advanced Packaging Design Video Series
In a significant move aimed at empowering semiconductor and systems-design engineers, MZ Technologies has announced the launch of a new video series focused on advanced packaging design. This initiative comes at a time when the semiconductor industry is rapidly shifting toward multi-die, 2.5D/3D integration, heterogeneous… Read More
