Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked… Read More
If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.
When 3D packaging was first introduced, there were not really any effective… Read More
Title: Mastering the Art of Managing IP, Chiplets, and Design Data
Date: Wednesday, November 1, 2023
Time: 10:00 AM Pacific Time
Duration: 30 minutes (+15 minutes live Q/A)
Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in
The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs,… Read More
Much of the recent Keysight EDA 2024 announcement focuses on high-speed digital (HSD) and RF EDA features for Advanced Design System (ADS) and SystemVue users, including RF System Explorer, DPD Explorer (for digital pre-distortion), and design elements for 5G NTN, DVB-S2X, and satcom phased array applications. Two important… Read More
The UCIe™ 1.1 Specification: Future Applications of Chiplets
Thursday, October 12, 2023
10 AM PT / 1 PM ET
Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel
The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification
Dan is joined by a panel of experts to discuss chiplets and 2.5/3D design. The panelists are: Saif Alam – Vice President of Engineering at Movellus Inc., Tony Mastroianni Siemens EDA- Advanced Packaging Solutions Director and Craig Bishop – CTO Deca Technologies.
In this spirited and informative discussion the … Read More
Date: Thursday, October 12, 2023
Time: 10:00am – 11:00am (PDT)
The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages… Read More
Semiconductor industry is going through an unprecedented technological revolution with AI/ML, GPU, RISC-V, chiplets, automotive and 5G driving the hardware design innovation. The race to deliver high performance, optimizing power and area (PPA), while ensuring safety and security is truly on. It has never been a more exciting… Read More
Harry Peterson is a mixed-signal chip designer with a BS in Physics from Caltech. He managed IC design groups within Fairchild, Kodak, Philips, Northern Telecom, Toshiba and Pixelworks. During sabbaticals he helped fly experiments on NASA’s orbiting satellite observatory (OSO-8) and build telescopes in the Canary… Read More
