Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.
The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS
Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types,
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification … Read More
Every few months, I touch base with Cristian Amitroaie, CEO of AMIQ EDA, to learn more about how AMIQ is helping hardware design and verification engineers be more productive. Quite often, his answers surprise me. When he started describing their Design and Verification Tools (DVT) Eclipse Integrated Development Environment… Read More
SystemVerilog (SV) has become the basis for verifying FPGA and ASIC designs. As the complexity of SOC designs grows, advanced verification methodology concepts such as: Constrained Random Stimulus, Functional Coverage, and Test Environment Reuse are needed at the system … Read More
I’ve enjoyed my past discussions with Cristian Amitroaie, the CEO of AMIQ EDA, in which we covered their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and their Verissimo SystemVerilog Testbench Linter. Cristian’s descriptions of AMIQ’s products and customers have intrigued me. They… Read More
It is important when talking about a market to first establish the need and potential growth, then determine how the market is being served. This requires examining product features and services offered. … Read More
This is it! This is the single page of code that Ákos Hadnagy wrote this summer to formally verify WARP-V, an open-source RISC-V CPU core.… Read More
A few months back, we interviewed Cristian Amitroaie, the CEO of AMIQ EDA. We talked mostly about their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and how it helps design and verification engineers develop code in SystemVerilog and several other languages. Cristian also mentioned… Read More
My usual practice when investing is to look at startup companies and try to understand if the market they are looking to serve has a significant opportunity for a new and disruptive technology. This piece compiles the ideas that I used to form an investment thesis in Portable Stimulus. Once collected, I often share ideas to get feedback.… Read More
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Teaching AI to be Evil with Unethical Data