The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More
Tag: systemverilog
SystemVerilog Has Some Changes Coming Up
SystemVerilog came to life in 2005 as a superset of Verilog-2005. The last IEEE technical committee revision of the SystemVerilog LRM was completed in 2016 and published as IEEE 1800-2017.
Have the last seven years revealed any changes or enhancements that maintain SystemVerilog’s relevance and efficaciousness in the face … Read More
Generative AI for Silicon Design – Article 1 (Code My FSM)
In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article… Read More
Using Linting to Write Error-Free Testbench Code
In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing… Read More
Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)
Time: 11:00 AM – 12:00 PM (PDT)
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More
The Inconvenient Truth of Clock Domain Crossings
Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More
AMIQ: Celebrating 20 Years in Consulting and EDA
We’re getting close to the annual July Design Automation Conference (DAC) in San Francisco, and every year I like to make the rounds of the exhibitors beforehand and see what’s new. When I checked with AMIQ EDA, I found that this is a big year for them. Their parent company AMIQ just reached its 20th anniversary, and they’ll be celebrating… Read More
DVCon China 2023
About DVCon China
DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon