SystemVerilog Has Some Changes Coming Up

SystemVerilog Has Some Changes Coming Up
by Daniel Payne on 11-29-2023 at 10:00 am

SystemVerilog - extending coverpoints

I first met Prabhu Goel at Wang Labs in 1982, then Prabhu and Phil Moorby went on to create Verilog at Gateway Design Automation in the early 80s, and finally their company was acquired by Cadence in 1990. Cadence created Open Verilog International (OVI) in 1991, transferring the language to the public domain, and then the IEEE  created… Read More


Generative AI for Silicon Design – Article 1 (Code My FSM)

Generative AI for Silicon Design – Article 1 (Code My FSM)
by Anshul Jain on 10-24-2023 at 10:00 am

Generative AI for Silicon Design

In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article… Read More


Using Linting to Write Error-Free Testbench Code

Using Linting to Write Error-Free Testbench Code
by Daniel Nenni on 08-23-2023 at 10:00 am

AMIQ EDA Design and Verification

In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing… Read More


Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)

Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)
by Admin on 08-07-2023 at 4:51 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)
by Admin on 08-07-2023 at 4:49 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)
by Admin on 08-07-2023 at 4:48 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am

Figure 3

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More


AMIQ: Celebrating 20 Years in Consulting and EDA

AMIQ: Celebrating 20 Years in Consulting and EDA
by Daniel Nenni on 07-06-2023 at 10:00 am

AMIQ20

We’re getting close to the annual July Design Automation Conference (DAC) in San Francisco, and every year I like to make the rounds of the exhibitors beforehand and see what’s new. When I checked with AMIQ EDA, I found that this is a big year for them. Their parent company AMIQ just reached its 20th anniversary, and they’ll be celebrating… Read More


CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance

CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
by Admin on 06-02-2023 at 1:46 pm

Date: Wednesday, June 7, 2023

Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST

Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows.  Built on a SystemVerilog… Read More