TrueChip CXL Verification IP

TrueChip is a Verification IP specialist. For more than 10 years they have provided verification IP’s, like USB, PCIe, Ethernet, Memory, AMBA, Display RISC V and many more. They have an extensive portfolio including a very interesting product that is “TruEYE™️ GUI” which is a debugger helper tool for the verifications IPs.

Protocol Intro

The CXL standard is an extension of the PCI Express standard, implementing some more features, but staying compatible. CXL (Compute Express Link) is an open interconnect standard for enabling efficient, coherent memory accesses between a host, such as a CPU, and a device, such as a hardware accelerator, that is handling an intensive workload.

“CXL is a new interconnect for device connectivity, which aims to remove bottlenecks between CPU and high bandwidth devices or memory subsystems, such as accelerators with large memory (graphics cards, GPUs based accelerator devices), memory extension devices and accelerators without much memory (NIC, FPGA based devices)”, said Nitin Kishore, CEO, Truechip.

He further added, “CXL acts as an efficient interconnect between the CPU and workload accelerators to enable high-speed communications, which is the vital need of emerging applications such as Artificial Intelligence and Machine Learning. With the release of CXL Verification IP, our goal is to enable designers to efficiently verify the latest accelerator devices and subsystems.”

CXL is expected to be implemented in heterogenous computing systems that include hardware accelerators that are addressing topics in artificial intelligence, machine learning, and other specialist tasks. The technology is built upon the well-established PCI Express® (PCIe®) infrastructure, leveraging the PCIe 5.0 physical and electrical interface to provide advanced protocol in three key areas:

• I/O Protocol
• Memory Protocol, initially allowing a host to share memory with an accelerator
• Coherency Interface

CXL uses three protocols: CXL.io, CXL.cache, and CXL.mem. The CXL.io protocol is used for initialization and link-up, so it must be supported by all CXL devices and appear in PCIe config space, with additional register capabilities.

TrueChip Verification IP

The architecture is show in figure below, and supports all possible device types in the standard.

The TrueChip CXL Verification IP will cover all CXL standard with some features like:

• Verification IP configurable as CXL Host and Device when operating in Flex Bus mode and as PCI Express Root Complex and Device Endpoint when operating in PCIe mode.
• Support for all three CXL protocols i.e., CXL.io, CXL.cache, CXL.mem and device types to meet specific application requirements with user configurable memory size for both CXL Host and Device.
• Support for Alternate Protocol Negotiation for CXL Mode.
• Support Pipe Specification 5.1 with both Low Pin Count and Serdes Architecture.
• Support for CXL Link Layer Retry Mechanism.
• Support for Configurable timeout for all three layers.
• Support for different CXL/PCIe Resets.
• Support for CXL 2.0 Configuration and Memory Mapped Registers(For CXL Device and Ports)
• Support for CXL ALMP transmission and reception to control virtual link state machine and power state transition requests.
• Support for CXL ACK forcing and Link Layer Credit exchange mechanism.
• Support Arbitration among the CXL.IO, CXL.cache and CXL.mem packets with Interleaving of traffic between different CXL protocols.
• Support for randomization and user controllability in flit packing.
• Support for power management including the low power L1 with sub-state and L2.
• Provides a comprehensive user API (callbacks).
• Built in Coverage analysis. (TruEYE™️ GUI)

The TrueChip Verification IP not only support a host device, but the slave device and beyond that also support three CXL device types as defined in the standard that is:

• Type 1 – CXL.io + CXL.cache
• Type 2 – CXL.io + CXL.cache + CXL.mem
• Type 3 – CXL.io + CXL.mem

So, this IP is a very powerful and complete solution if you are in need of the CXL protocol in your design and want it to be correct by construction the very first time.

To know more details you can check the webinar replay in the link below and check the Truechip website for more technical detail:

https://www.truechip.net/video/Final_CXL_Webinar.mp4

Also read:

Webinar Replay on TileLink from Truechip

Verification IP Coverage

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