Driven by the need to rapidly move data across a chip, the NoC IP is already a very common structure for moving data with an SoC. And various implementations of the NoC IP are available in the market depending on the end system requirements. Over the last few years, the RISC-V architecture and the TileLink interface specification have been gaining broad adoption. While the TileLink specification was originally developed to work with the RISC-V architecture, it actually supports other instruction set architectures (ISAs) too. The conjunction of these trends has created a need for a NoC IP to work with the TileLink protocol.
A recent SemiWiki post discussed the DisplayPort VIP solution from Truechip, an IP company that has been serving customers for more than a decade. While Truechip has established itself as a global provider of verification IP (VIP) solutions, they are always on the lookout for strategic IP needs from their customer base. Truechip has seized the above strategic NoC IP opportunity to develop a design IP targeting RISC-V based chips supporting the TileLink interface specification. Since its introduction to the market last year, this IP has been gaining a lot of adoption within Truechip’s customer base. While this is their first design IP addition to their product offering, we can expect to see more strategic additions in the future.
Truechip’s NoC Silicon IP
Truechip’s NoC silicon IP’s target applications are RISC-V based chip system implementations leveraging the TileLink specification. The IP provides chip architects and designers with an efficient way to connect multiple TileLink based master and slave devices for reduced latency, power, and area. And of course, it helps reduce physical interconnect routing and use of resources inside an SoC. The solution is offered in native Verilog. Truechip’s unique RTL coding technique has yielded a high quality IP that offers low latency, high throughput and takes very little silicon area. While the current version supports the TileLink Uncached Lightweight (TL-UL) and TileLink Uncached Heavyweight (TL-UH) conformance levels, the next version will include support for TL-C (cache coherency) conformance level.
Some Salient Features
- Supports N master and M slave ports as per customer requirements
- Supports wide range of memory map
- Supports both little endianness and big endianness
- Supports both the TL-UL and TL-UH conformance levels
- Supports all TileLink networks that follow a directed acyclic graph (DAG)
- Supports configurable widths of various parameters of data and address bus
- Supports all types of operations per conformance levels
- Can work as any node of a graph tree
- Tip (with no branches)
- Tip (with branches)
NoC Silicon IP in RTL form
Testbench and Sanity Tests
User Manual and Integration guide
Quick start guide
TruEye Tool for debug (optional)
Full Verification IP for TileLink (optional)
Truechip, the Verification IP specialist, is a leading provider of Design and Verification solutions. It has been serving customers for more than a decade. Its solutions help accelerate the design cycle, lowers the cost of development and reduces the risks associated with the development of ASICs, FPGAs, and SoCs. The company has a global footprint with sales coverage across North America, Europe and Asia. Truechip provides the industry’s first 24×7 support model with specialization in VIP integration, customization and SoC Verification.
For more information, refer to Truechip website.