Chiplets at the Design Automation Conference with OpenFive

Chiplets at the Design Automation Conference with OpenFive
by Daniel Nenni on 08-02-2022 at 10:00 am

OpenFive Chiplet 59DAC

SemiWiki has been tracking the popularity of chiplets for two years now so it was not surprising to see that they played a key role at DAC. The other trend we foresaw was that the ASIC companies would be early chiplet adopters and that has proven true. One of the more vocal proponents of chiplets at DAC#59 was OpenFive, a 17+ year spec-to-silicon… Read More


Post-quantum cryptography steps on the field

Post-quantum cryptography steps on the field
by Don Dingee on 08-01-2022 at 6:00 am

PQSubSys post quantum cryptography IP

In cybersecurity circles, the elephant in the room is a quantum computer in the hands of nefarious actors. A day is coming, soon, when well-funded organizations will be able to rent time on, or maybe even build or buy a quantum machine. Then, if data is valuable enough, people will hunt for it. Two or three months of compute time on a … Read More


Axiomise at #59DAC, Formal Update

Axiomise at #59DAC, Formal Update
by Daniel Payne on 07-27-2022 at 10:00 am

Dr. Ashish Darbari min 1

Monday at DAC I was able to meet with Dr. Ashish Darbari, the CEO and founder of Axiomise. Ashish had a busy DAC, appearing as a panelist at,  “Those Darn Bugs! When Will They be Exterminated for Good?”; and then presenting,  “Taming the Beast: RISC-V Formal Verification Made Easy.”

I had read a bit about Axiomise… Read More


Jade Design Automation’s Register Management Tool

Jade Design Automation’s Register Management Tool
by Kalar Rajendiran on 07-05-2022 at 10:00 am

RegMan supervisor CSRs

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential… Read More


Using an IDE to Accelerate Hardware Language Learning

Using an IDE to Accelerate Hardware Language Learning
by Daniel Nenni on 06-29-2022 at 10:00 am

Indian Institute of Technology IIT Bhubaneswar

Recently, in one of my regular check-ins with AMIQ EDA, I was pleased that they linked me up with an active customer. The resulting post summarized my discussion with three engineers from Kepler Communications Inc. They talked about using one of the AMIQ EDA products in the design of FPGAs for space-borne Internet connectivity.… Read More


Podcast: Will Arm Risk RISC-V?

Podcast: Will Arm Risk RISC-V?
by Daniel Nenni on 06-15-2022 at 6:00 am

What’s at stake? A candid discussion between Junko Yoshida, Editor in Chief of the Ojo-Yoshida Report, and Frank Lin, CEO of Andes.

Will Arm RISC-V? from the Ojo-Yoshida Report

Andes Technology, a Taiwanese CPU core IP company, began phasing out its proprietary processing architecture in favor of RISC-V in 2015, as it preparedRead More


Truechip’s Network-on-Chip (NoC) Silicon IP

Truechip’s Network-on-Chip (NoC) Silicon IP
by Kalar Rajendiran on 06-14-2022 at 10:00 am

Truechip NoC Silicon IP Block Diagram

Driven by the need to rapidly move data across a chip, the NoC IP is already a very common structure for moving data with an SoC. And various implementations of the NoC IP are available in the market depending on the end system requirements. Over the last few years, the RISC-V architecture and the TileLink interface specification … Read More


RISC-V embedded software gets teams coding faster

RISC-V embedded software gets teams coding faster
by Don Dingee on 06-07-2022 at 10:00 am

Nucleus RTOS

RISC-V processor IP is abundant. Open-source code for RISC-V is also widely available, but typically project-based code solves one specific problem. Using only pieces of code, it’s often up to a development team integrate a complete application-ready stack for creating an embedded device. A commercial embedded software development… Read More


Scaling is Failing with Moore’s Law and Dennard

Scaling is Failing with Moore’s Law and Dennard
by Dave Bursky on 05-12-2022 at 6:00 am

Scaling is Falling SemiWiki

Looking backward and forward, the white paper from Codasip “Scaling is Failing” by Roddy Urquhart provides an interesting history of processor development since the early 1970s to the present. However it doesn’t stop there and continues to extrapolate what the chip industry has in store for the rest of this decade. For the last… Read More


CEO Interviews: Dr Ali El Kaafarani of PQShield

CEO Interviews: Dr Ali El Kaafarani of PQShield
by Daniel Nenni on 05-06-2022 at 6:00 am

Dr Ali El Kaafarani Profile Picture

Dr Ali El Kaafarani is the founder and CEO of PQShield, a British cybersecurity startup specialising in quantum-secure solutions. A University of Oxford spin-out, PQShield is pioneering the commercial roll-out of a new generation of cryptography that’s fit for the quantum challenge, yet integrates with companies’ legacy

Read More