Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More


WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

UVM Testbench RISC-V

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More


RISC-V Day, the leading RISC-V conference, comes to Vietnam in this September!

RISC-V Day, the leading RISC-V conference, comes to Vietnam in this September!
by Daniel Nenni on 09-18-2020 at 8:00 am

RISC-V Day Vietnam 2020 Online is the largest RISC-V conference in Vietnam. RISC-V suppliers deliver their technical PR and RISC-V researchers present their research results. In the fields of IoT applications involving AI, security and others presenting excellent technologies and products related to RISC-V. Key persons … Read More


CORE-V HW and SW in the FPGA environment

CORE-V HW and SW in the FPGA environment
by Daniel Nenni on 08-20-2020 at 11:00 am

Episode 3 of OpenHW TV will air live on 20th August at 11am EST / 4pm BST / 8am PST and will give a detailed update of work in our HW and SW Task Groups, as well as featuring guest member Ashling.

You will hear from the Chairs of the groups about the work of the SW and HW Task Groups to date, including an outlook to future roadmaps. We look

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Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation.’

Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation.’
by Daniel Nenni on 07-15-2020 at 8:00 am

☕️ Join the latest webinar with RISC-V international members Andes, Imperas, and UltraSoC on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs, covering early SW development, HW verification and analysis for system level design optimization.

Part #1 of our AI & ML webinar series focused on architecture. … Read More


Interface IP Category to Overtake CPU IP by 2025?

Interface IP Category to Overtake CPU IP by 2025?
by Eric Esteve on 07-09-2020 at 6:00 am

Top 5 Forecast 2020 2024

The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More