Maven Silicon’s RISC-V Processor IP Verification Flow

Maven Silicon’s RISC-V Processor IP Verification Flow
by Sivakumar PR on 02-24-2023 at 6:00 am

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RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized accelerators and optional standard extensions to support general-purpose software development. RISC-V supports both 32-bit and … Read More


Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard

Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard
by Admin on 12-30-2022 at 11:51 am

With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and

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CHIPS Alliance, Fall Technology Update

CHIPS Alliance, Fall Technology Update
by Admin on 12-14-2022 at 1:43 pm

SUNNYVALE, CA + VIRTUAL

Join us in-person for our second biannual technology update featuring informative, technical talks on open source hardware collaborative development, hosted by Google and including speakers from Microsoft, Google, Intel, Antmicro, Efabless and others.

CHIPS’ Thursday event follows the main RISC-V

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VeriSilicon’s VeriHealth Chip Design Platform for Smart Healthcare Applications

VeriSilicon’s VeriHealth Chip Design Platform for Smart Healthcare Applications
by Kalar Rajendiran on 12-13-2022 at 10:00 am

VeriHealth Showing Fall Detection

The wearables electronics market is a large and fast growing one. According to Precedence Research, the global wearable technology market is expected to grow at a compound annual growth rate of 13.89% during the forecast period 2022 to 2030. Precedence estimated the global wearable technology market size at USD 121.7 billion… Read More


Re-configuring RISC-V Post-Silicon

Re-configuring RISC-V Post-Silicon
by Bernard Murphy on 12-07-2022 at 6:00 am

Post Silicon RISC V extensions min

How do you reconfigure system characteristics? The answer to that question is well established – through software. Make the underlying hardware general enough and use platform software to update behaviors and tweak hardware configuration registers. This simple fact drove the explosion of embedded processors everywhere … Read More


Is your career at RISK without RISC-V?

Is your career at RISK without RISC-V?
by Sivakumar PR on 12-05-2022 at 6:00 am

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I am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the future of the open era of computing. If you understand how we build complex electronic devices like desktops and smartphones using processors, you would be more interested in learning and… Read More


DVClub Europe Meeting: RISC-V Verification Strategies

DVClub Europe Meeting: RISC-V Verification Strategies
by Admin on 11-21-2022 at 1:20 pm

Tuesday 29th November, 2022

12:00 – 13:30 GMT

RISC-V Verification Strategies

With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC.

About DVClub

The principal

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