Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation.’

Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation.’
by Daniel Nenni on 07-15-2020 at 8:00 am

☕️ Join the latest webinar with RISC-V international members Andes, Imperas, and UltraSoC on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs, covering early SW development, HW verification and analysis for system level design optimization.

Part #1 of our AI & ML webinar series focused on architecture. … Read More


Interface IP Category to Overtake CPU IP by 2025?

Interface IP Category to Overtake CPU IP by 2025?
by Eric Esteve on 07-09-2020 at 6:00 am

Top 5 Forecast 2020 2024

The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More


RISC-V Formal Verification for ISA Compliance

RISC-V Formal Verification for ISA Compliance
by Daniel Nenni on 07-07-2020 at 10:00 am

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RISC-V is an open standard instruction set architecture introduced in 2010. It has experienced exponential growth in recent years, enabling users to design custom processors more quickly and cost effectively to meet today’s demand for more technological innovations in the CPU, GPU, AI, ML spaces.

However, verification of … Read More


SiFive’s Approach to Embedding Intelligence Everywhere

SiFive’s Approach to Embedding Intelligence Everywhere
by Tom Simon on 04-27-2020 at 6:00 am

SiFive Embedding Intelligence

Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years.  RISC-V was conceived with a clean… Read More


Verification, RISC-V and Extensibility

Verification, RISC-V and Extensibility
by Bernard Murphy on 02-05-2020 at 6:00 am

RISC-V

RISC-V is obviously making progress. Independent of licensee signups and new technical offerings, the simple fact that Arm is responding – in fundamental changes to their licensing model and in allowing custom user extensions to the instruction set – is proof enough that they see a real competitive threat from RISC-V.

Which all… Read More


SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!
by Swamy Irrinki on 11-14-2019 at 2:00 pm

We’re confirming seats in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga for the South American leg of our worldwide 2019 SiFive Tech Symposiums and Workshops. These five events will be focused heavily on academia, which is a key focus for SiFive. In fact, we are co-hosting these events with many of the most prestigious… Read More