RISC-V Days Tokyo 2022by Admin on 05-31-2022 at 12:00 am
May 31, 2022 / 12:50 〜 19:00
June 1, 2022 / 10:00 〜 17:00
June 2, 2022 / 10:00 〜 16:00
Japan Standard Time (UTC+9)
RISC-V Days Tokyo is Japan’s largest online RISC-V event. Live online presentations are hosted on May 31st (Tue), June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days.… Read More
Looking backward and forward, the white paper from Codasip “Scaling is Failing” by Roddy Urquhart provides an interesting history of processor development since the early 1970s to the present. However it doesn’t stop there and continues to extrapolate what the chip industry has in store for the rest of this decade. For the last… Read More
Spring 2022 RISC-V Weekby Admin on 05-03-2022 at 12:00 am
The Spring 2022 RISC-V Week will be held at the Auditorium of the Centre International de Conférences on the Jussieu Campus in Paris. It will take place May 3-5, 2022.
After the disruptions of the 2020/2021 editions due to the pandemic, we are happy to hold the Spring 2022 edition in real life and resume the great networking experience… Read More
From a business viewpoint we often read in the technical press about the virtues of applying AI, and in the early days most of the AI model building was done in the cloud, because of the high computation requirements, yet there’s a developing trend now to use AI accelerators at the Edge. The other mega-trend in the past decade… Read More
India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”.
To introduce RISC-V, it is a free and … Read More
Success with Open-Source Formal Verification
The dream of 100% confidence is compelling for silicon engineers. We all want that big red button to push that magically finds all of our bugs for us. Verification, after all, accounts for roughly two-thirds of logic design effort. Without that button, we have to create reference models,… Read More
Imperas RISC-V reference models highlighted for software development and RISC-V processor verification, including an example project with NSITEXE.
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with eSol Trinity the webinar event on RISC-V reference models and simulation technology… Read More
We will have a number of interesting speakers and also give a RISC-V overview! As it is a virtual conference we will make it 2h.
We plan some Q&A, you can submit questions during the presentation and we will answer them via chat or live from the speaker.… Read More
Frankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working… Read More
