The extremely popular RISC-V instruction set architecture (ISA) originally came from the Berkeley Architecture Research (BAR) group. BAR also developed several other key pieces of enabling technology that have helped RISC-V become so popular. Among these are Rocket Chip which serves as a RISC-V based SOC generator. It can generate multi-core systems with Rocket scalar cores, Z-Scale control processors, and a coherent memory system. The last item on that list, a coherent memory system, is an absolute necessity for these SOCs. Which brings us to another fascinating BAR project – TileLink. To cite BAR’s own description: Tile Link is a protocol designed to be a substrate for cache coherence transactions implementing a particular cache coherence policy within an on-chip memory hierarchy.
Anyone building a RISC-V SOC, and perhaps many other kinds as well may want to include TileLink as the protocol for implementing memory coherence. It offers many features that make it an excellent choice. Truechip, a leading provider of verification intellectual property (VIP) has recently posted a webinar replay on TileLink and the VIP that True Chip provides to ensure system level compatibility with all the attached memory subsystem agents. The protocol is designed, when implemented properly, to prevent deadlocks. There are five unidirectional channels, each with a specified priority that makes this possible. TileLink can be used with clients that do not have their own cache or can be used to connect standalone caches to clients. Any arrangement of agents is allowed so long as they form an acyclic directed graph (DAG).
The Truechip webinar goes through the details of the transactions on TileLink and explains the various options available for sharing data. TileLink supports data transfers with a size equivalent to the bus width, or multiple bus widths using what are called beats. Responses to operations are not necessarily ordered. The webinar also offers a comparison of TileLink with other potential interfaces such as AHB, Wishbone, AXI4, ACE and CHI.
The Truechip VIP works by establishing a monitor that can observe master/slave communication and then connects to a scoreboard. When scaling up, the monitor can be connected to a cross bar to allow multiple slave/monitor environments. The VIP supports all three conformance levels, TL-UL, TL-UH and TL-C. The True Chip VIP supports complex network structures, so long as they conform to a DAG. All aspects of TileLink are parameterized to support any configuration. The Truechip VIP also supports permission transitions, busy and wait states, various memory maps, response generation & ordering.
Truechip has developed their TruEYE™ graphical interface to assist in debugging and monitoring transactions. TruEYE™ offers tabular and graphical views. For instance, in the case of TileLink transactions, columns are set up with a timestamp, Channel, VALID, READY, SOURCE ADDRESS, OPCODE, PARAMETER, etc. Each transaction can be examined in detail. The test environment and test suite can include basic and directed protocol tests, random tests, error scenario tests, RAL tests, dynamic tests, and assertions & cover point tests.
I recommend the webinar for anyone looking for more insight into building and verifying TileLink interfaces. RISC-V has changed the landscape for SOC design, making it possible to take robust and well-designed elements and build sophisticated SOCs. It’s nice to know that there is good support in the industry for these new specifications. True Chip has amazing wide support for many interfaces, including of course TileLink. The webinar and more information are available on the Truechip website www.truechip.net