CEO Interview: Deepak Kumar Tala of SmartDV

CEO Interview: Deepak Kumar Tala of SmartDV
by Daniel Nenni on 06-22-2020 at 10:00 am

SmartDV CEO Interview 2020

SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely. They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification IP… Read More


SemiWiki and SmartDV on Verification IP

SemiWiki and SmartDV on Verification IP
by Daniel Nenni on 06-06-2018 at 7:00 am

Bernard Murphy and I spent time with the SmartDV folks in preparation for the Design Automation Conference later this month. Bernard is an internationally recognized verification expert so his feedback is often sought after by emerging and leading verification companies, absolutely. Verification IP is a crowded market so … Read More


ARM and Cadence IP Simplify IoT System Design and Verification

ARM and Cadence IP Simplify IoT System Design and Verification
by Mitch Heins on 08-01-2017 at 7:00 am

As the Internet-of-Things (IoT) markets mature, we are seeing the complexity of IoT systems evolve from simple routing functions that connect IoT edge devices to the cloud into more complex system of systems that manage the interaction between multiple sensor-hubs. IoT sensor-hubs and gateways not only take care of basic care… Read More


Mentor Extends Verification Offering!

Mentor Extends Verification Offering!
by Daniel Nenni on 03-14-2016 at 12:00 pm

With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better… Read More


Synopsys VC VIP for Memory

Synopsys VC VIP for Memory
by Paul McLellan on 09-04-2014 at 7:01 am

Synopsys have been gradually broadening their portfolio of verification IP (VIP). It is 100% native SystemVerilog with native debug using Verdi (that was acquired from SpringSoft last year, now fully integrated into Verification Compiler). It has native performance with VCS. Going forward there are source code test suites.… Read More


PCI Express 4 specification just released for PCI-SIG DevCon

PCI Express 4 specification just released for PCI-SIG DevCon
by Eric Esteve on 07-01-2014 at 4:45 am

I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members’ review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP… Read More


You can tune a piano, but you can’t tune a cache without help

You can tune a piano, but you can’t tune a cache without help
by Don Dingee on 05-30-2013 at 8:30 pm

Once upon a time, designing a product with a first generation SoC on board, we were trying to use two different I/O peripherals simultaneously. Seemed simple enough, but things just flat out didn’t work. After days spent on RTFM (re-reading the fine manual), we found ourselves at the absolute last resort: ask our FAE.

After about… Read More


In compliance we trust, for integration we verify

In compliance we trust, for integration we verify
by Don Dingee on 03-26-2013 at 8:10 pm

So, you dropped that piece of complex IP you just licensed into an SoC design, and now it is time to fire up the simulator. How do you verify that it actually works in your design? If you didn’t get verification IP (VIP) with the functional IP, it might be a really long day.

Compliance checking something like a PCIe interface block is a … Read More


Cadence sets the Global Standards in VIP for AMBA based SoC

Cadence sets the Global Standards in VIP for AMBA based SoC
by Eric Esteve on 11-12-2012 at 11:48 am

We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More


Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards

Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards
by Eric Esteve on 09-27-2011 at 1:56 am

The mobile devices market is simply exploding, with smartphones shipmentgoing up to the sky, tabletsemerging so fast that some people think it will replace PC (but this is still to be confirmed…). This lead mobile SoC designs to integrate increasingly more features, to support customer needs for more computing power and sophisticated… Read More